Semiconductor memory device

Abstract

In a semiconductor memory device comprising memory cells in which first and second potentials correspond to the logic values "0" and "1", the first potential is closer to the second potential than the potential of unselected word lines, by 0.3 V or more. The pull-up transistor is of the N-type, and the pull-down transistor is of the P-type.

What is claimed is: 
     
       1. A semiconductor device comprising: a plurality of memory cells capable of being selected for use or remaining unselected, at least one unselected memory cell .[.having a logical value of "0" and.]. having a first signal voltage potential .Iadd.corresponding to a first logical value.Iaddend.;   at least one selected memory cell .[.having a logical value of "1" and.]. having a second signal voltage potential .Iadd.corresponding to a second logical value.Iaddend.;   a first .[.set of reading and restoring.]. word .[.lines.]. .Iadd.line .Iaddend.connected to selected memory cells, said first .[.set of.]. word .[.lines.]. .Iadd.line .Iaddend.having a signal voltage potential which is higher than said second signal voltage potential by a first predetermined value; and   a second .[.set of.]. word .[.lines.]. .Iadd.line .Iaddend.connected to unselected memory cells, said second .[.set of.]. word .[.lines.]. .Iadd.line .Iaddend.having a signal voltage potential which is .[.higher.]. .Iadd.lower .Iaddend.than said first signal voltage potential by a second and different predetermined value.   
     
     
       2. A semiconductor memory device according to claim 1, wherein said second and different predetermined value is 0.3 V or more. .Iadd. 
     
     
       3.  The semiconductor memory device of claim 1 comprising a sense circuit to which first and second bit lines are connected at first and second nodes, respectively, said sense circuit comprises: a first MOS transistor of a first conductivity type connected between a first voltage line and a third node;   second and third MOS transistors of the first conductivity type, the source and drain of said second MOS transistor being connected between said first and third nodes, the source and drain of said third MOS transistor being connected between said second and third nodes;   a fourth MOS transistor of the first conductivity type connected between a second voltage line and a fourth node; and   fifth and six MOS transistors of a second conductivity type, the source and drain of said fifth MOS transistor being connected between said first and fourth nodes, the source and drain of said sixth MOS transistor being connected between said second and fourth nodes;   the gate of said second and fifth MOS transistors being connected to said second node, the gate of said third and sixth MOS transistors being connected to said first node. .Iaddend..Iadd.4. The semiconductor memory device of claim 1 comprising a sense circuit to which first and second bit lines are connected at first and second nodes, respectively, said sense circuit comprises:   a first MOS transistor of a first conductivity type connected between a first voltage line and a third node;   second and third MOS transistors of a second conductivity type, the source and drain of said second MOS transistor being connected between said first and third nodes, the source and drain of said third MOS transistor being connected between said second and third nodes;   a fourth MOS transistor of the second conductivity type connected between a second voltage line and a fourth node; and   fifth and sixth MOS transistors of the first conductivity type, the source and drain of said fifth MOS transistor being connected between said first and fourth nodes, the source and drain of said sixth MOS transistor being connected between said second and fourth nodes;   the gate of said second and fifth MOS transistors being connected to said second node, the gate of said third and sixth MOS transistors being connected to said first node. .Iaddend.