Bipolar-MOS comparator circuit with saturation prevention

Abstract

An electronic comparator circuit having a high speed during switch phase and combining the advantages of bipolar technology with those of CMOS technology. The circuit consists of a differential stage input circuit having a differential pair of bipolar transistors forming its outputs. The output stage contains a pair of MOS transistors having gate electrodes in common. The pair of MOS transistors is connected on one side to the outputs of the input portion and on the other side to a positive supply pole via a current mirror circuit. The output contains another pair of MOS transistors with gate electrodes in common connected between the out puts of the input portion and ground. The drain electrode of the first pair of MOS transistors forms the output for the comparator.

We claim: 
     
       1. An electronic comparator circuit of a type which comprises a first, differential stage input circuit portion provided with a differential pair of bipolar transistors with collectors constituting respective outputs of said input portion, characterized in that it incorporates an output stage comprising a first pair of MOS transistors, with gate electrodes in common, being respectively connected on the one side to said outputs and on the other side to a positive supply pole via a current mirror circuit, and a second pair of MOS transistors, with gate electrodes in common, being connected between said outputs and ground, a drain electrode of said first pair of MOS transistors forming an output terminal for the comparator. 
     
     
       2. A circuit according to claim 1, characterized in that said first pair of MOS transistors are connected into a cascade configuration connected to the outputs of the bipolar transistor pair. 
     
     
       3. A circuit according to claim 1, characterized in that said output stage comprises a further MOS transistor connected in diode configuration between the gates of said first pair of MOS transistors and ground, via a resistor, and with the gate electrode connected directly to the gates of said second pair of MOS transistors. 
     
     
       4. A circuit according to claim 1, characterized in that said mirror current circuit comprises a further pair of MOS transistors, of which one is in a diode configuration, and is inserted between said positive supply pole and the drain electrodes of said first pair of MOS transistors. 
     
     
       5. A circuit according to claim 1, characterized in that said first input circuit portion has a signal input and a threshold input respectively associated with corresponding bipolar transistors connected into an emitter follower configuration between ground and said differential stage. 
     
     
       6. A circuit according to claim 1, characterized in that it includes a bias current source between said positive supply pole and the gates of said first pair of MOS transistors. .Iadd. 
     
     
       7.  A comparator circuit, comprising: a differential pair having a first bipolar transistor and a second bipolar transistor with an emitter of the first bipolar transistor electrically connected to an emitter of the second bipolar transistor,   a biasing circuit for biasing the differential pair so as to preclude the differential pair from operating in saturation mode, said biasing circuit including a first MOS transistor and a second MOS transistor forming a current source respectively connected to a collector of the first bipolar transistor and to a collector of the second bipolar transistor, and   a MOS transistor arrangement connected to the collectors of the first and second bipolar transistors, a drain of the MOS transistor arrangement providing an output of the comparator circuit, the MOS transistor arrangement being biased to a conductive state by a second biasing circuit. .Iaddend..Iadd.8. The comparator circuit of claim 7 wherein the second biasing circuit includes a resistor circuit connected to gate of   
     
     
        the MOS transistor arrangement. .Iaddend..Iadd.9.  A comparator circuit, comprising: a differential pair input section having a first and a second bipolar transistor, the differential pair receiving an input signal and a comparison signal; and   a MOS circuit section for biasing the first and second bipolar transistors to prevent the first and second bipolar transistors from entering saturation mode, the MOS circuit section including means for following the collector current of the first bipolar transistor so as to provide an output signal of the comparator circuit;   wherein the means for following includes a first MOS transistor having a source connected to the collector of the first bipolar transistor and having its gate voltage biased to place the first MOS transistor in a conductive state, and wherein the drain of the first MOS transistor   
     
     
        provides the output signal. .Iaddend..Iadd.10.  The comparator circuit of claim 9 wherein the MOS circuit section comprises a current source circuit connected to the collector of the first bipolar transistor and the collector of the second bipolar transistor. .Iaddend..Iadd.11. The comparator circuit of claim 10 further including a second MOS transistor having a source connected to the collector of the second bipolar transistor, the first MOS transistor and the second MOS transistor having their gates electrically connected together. .Iaddend..Iadd.12. The comparator circuit of claim 7 wherein the biasing circuit further includes a third MOS transistor with the drain and gate of the third MOS transistor electrically connected to a gate of the first MOS transistor and a gate of the second MOS transistor. .Iaddend..Iadd.13. The comparator circuit of claim 10 wherein the current source circuit includes a third, fourth, and fifth MOS transistor connected in a current mirror multiplier arrangement, with the third and fourth MOS transistors providing collector current that is a multiple of the collector current of the fifth MOS transistor. .Iaddend.