High speed analog-to-digital converter using cells with back-to-back capacitors for both rough and fine approximation

Abstract

A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

We claim: 
     
       1. .[.High.]. .Iadd.A high .Iaddend.speed analog-to-digital converter, .[.characterized in that it comprises.]. .Iadd.comprising; .Iaddend. a plurality of comparison cells which in successive steps determine the .[.four.]. most significant bits of the conversion and then.Iadd.,.Iaddend..[.the four least significant bits.]. after the more significant bits have been reconverted to analog and .[.their subsequent subtraction.]. .Iadd.subtracted .Iaddend.from the input signal.Iadd., the least significant bits;.Iaddend.   .[.where.]. .Iadd.wherein .Iaddend.each .[.of.]. said comparison .[.cells is constituted by.]. .Iadd.cell comprises .Iaddend.   a comparator .[.with.]. .Iadd.having an .Iaddend.input connected to an intermediate branch point between .[.two.]. .Iadd.first and second .Iaddend.condensers in series,   .[.one of which is .]. .Iadd.said first condenser being .Iaddend.supplied in a first step with an input signal,   in a second step with a first reference voltage different for each cell.Iadd., .Iaddend.and   in a third step with a selected reference voltage equal to .[.that.]. .Iadd.the one .Iaddend.of said first reference voltages which approximates said input signal .[.downward.]. .Iadd.from below .Iaddend.with the highest accuracy, .[.and by a.].   .Iadd.said second .Iaddend.condenser .[.which is.]. .Iadd.being .Iaddend.grounded during said first and second step.Iadd.s .Iaddend., .Iadd.and connected, during said .Iaddend..[.while in the.]. third step.Iadd., .Iaddend..[.it is connected.]. to .Iadd.a respective .Iaddend.one .[.respective.]. of a plurality of second reference voltages .Iadd.which are .Iaddend.submultiples of said first reference voltage.   
     
     
       2. .[.Converter.]. .Iadd.A converter .Iaddend.according to .[.Claim.]. .Iadd.claim .Iaddend.1, further comprising .[.a.]. decoding logic which detects the value of the outputs of said comparators during said second step.Iadd.,.Iaddend.and .Iadd.accordingly .Iaddend.determines during said third step the choice of said selected reference voltage..Iadd.3. The converter of claim 1, wherein said comparator is a single-input comparator..Iaddend..Iadd.4. The converter of claim 1, further comprising a shorting switch connected to short together an input with an output of said comparator during said first step..Iaddend..Iadd.5. The converter of claim 1, comprising 15 of said cells..Iaddend..Iadd.6. An integrated data conversion circuit, comprising:.Iaddend. a plurality of comparison cells, each including first and second capacitors each having a respective first terminal connected to a common node.     a thresholding logic circuit connected to provide a digital output corresonding to the analog voltage of said common node   a first initializing switch connected to selectably connect a second terminal of said first capacitor to an analog input voltage, and a second initializing switch connected to selectably connect a second terminal of said second capacitor to a constant voltage, a reference-connecting switch connected to selectably connect said second terminal of said first capacitor to a particular respective corresponding rough-approximation reference voltage, and a first fine-approximation switch connected to selectably connect said second terminal of said first capacitor to a common rough-approximation line, and a second fine-approximation switch connected to selectably connect said second terminal of said second capacitor to a particular respective corresponding fine-approximation reference voltage which is smaller in magnitude than said particular respective corresponding rough-approximation reference voltage; and   control logic connected to receive the outputs of said thresholding logic circuits, and connected to activate said initializing switches in a first phase, said reference-connecting switch in a second phase, and said fine-approximation switches in a third phase, and, during said second phase, to connect, to said rough-approximation line, one of said rough-approximation reference voltages which is selected in dependence on the outputs of said thresholding logic circuits after said first phase;   whereby the outputs of said thresholding logic circuits provide a two-stage digital output corresponding to said analog input signal..Iadd.7. The integrated circuit of claim 6, wherein said thresholding logic circuit is a single-input comparator..Iaddend..Iadd.8. The integrated circuit of claim 6, further comprising an additional respective switch between each said rough-approximation reference voltage and said rough-approximation line, and wherein said control logic is connected to activate a selected one of said additional switches during said second   
     
     
        phase..Iaddend..Iadd.    The integrated circuit of claim 6, further comprising a first resistor ladder which supplies said rough-approximation reference voltages from multiple nodes thereof, and a second resistor ladder which supplies said fine-approximation reference voltages from multiple nodes thereof..Iaddend..Iadd.10. The integrated circuit of claim 6, comprising exactly 15 of said comparison cells..Iaddend..Iadd.11. A method for analog-to-digital data conversion, comprising: providing a plurality of comparison cells, each including first and second capacitors each having a respective first terminal connected to a common node, and a thresholding logic circuit connected to provide a digital output dependent on the analog voltage of said common node,   during a first phase, connecting an analog input voltage to a second terminal of each said first capacitor, and connecting a second terminal of each said second capacitor to ground;   during a second phase, connecting a different respective one of a first set of reference voltages to said second terminal of each said first capacitor;   selecting a rough-approximation voltage in dependence on the outputs of said thresholding logic at the end of said second phase; and   during a third phase, connecting said rough-approximation voltage to said second terminals of all of said first capacitors, and connecting a different respective one of a second set of reference voltages to said second terminal of each said second capacitor; and   outputting bits corresponding to said outputs of said thresholding logic at the end of said second phase as more significant bits, and outputting bits corresponding to said outputs of said thresholding logic at the end of said third phase as less significant bits, to provide a digital value corresponding to said analog input value..Iaddend..Iadd.12. The method of claim 11, wherein, during said second phase, said second set of reference voltages provides four bits of additional resolution with respect to said first reference voltages..Iaddend..Iadd.13. The method of claim 11, wherein said first set of reference voltages is provided by a first resistor ladder, and said second set of reference voltages is provided by a second resistor ladder..Iaddend..Iadd.14. The method of claim 11, wherein said selecting step is performed by control logic which is connected to receive the outputs of each said thresholding logic circuit..Iaddend..Iadd.15. The method of claim 11, wherein said thresholding logic circuit is a single-input comparator..Iaddend.