Switching matrix crosspoint

Abstract

A crosspoint for a switching matrix constituted by enhanced P-channel and N-channel MOS transistors. Each input line conductor (Ii1 and Ii2) is connected to an input of a first differential amplifier (M3, M4), each leg of which is associated by a current mirror circuit to a first current source (M9, M10, M11) enabled by a selection input (Sij) of the crosspoint. The outputs of the first differential amplifier are connected to a second differential amplifier (M1, M2) fed by a second current source (I) common to all the crosspoints of a same column. The outputs of the second differential amplifier are connected to the pair of conductors (Oj1, Oj2) of an output column, an extremity of this column being connected to the high voltage source (Vdd) through a resistor (R).

I claim: 
     
       1. A crosspoint for a switching matrix having n input lines .[.(rows).]. and m output lines .[.(columns).]., each line comprising a pair of conductors, said crosspoint comprising .[.enhanced.]. P-channel and N-channel MOS transistors, wherein: each input line conductor .[.(Ii1 and Ii2).]. is connected to an input of a first differential amplifier .[.(M3, M4).]., each leg of which is associated by a current mirror circuit to a first current source .[.(M9, M10, M11).]. enabled by a selection input .[.(Sij).]. of said crosspoint.   the outputs of the first differential amplifier are connected to a second differential amplifier .[.(M1, M2).]. fed by a second current source .[.(I).]. common to all the crosspoints of a selected output line, and   the outputs of the second differential amplifier are connected to said selected output line, an extremity of which is connected to a high voltage source .[.(Vdd).]. through a .[.resistor (R).]. .Iadd.load element.Iaddend..   
     
     
       2. A crosspoint according to claim 1, further comprising means .[.(M8, Sij).]. for setting the voltage at the output of said first differential amplifier when said crosspoint is not selected. 
     
     
       3. A crosspoint according to claim 2, wherein said means for setting the voltage comprises a fourth N-channel transistor .[.(M8).]. connected in parallel to the third N-channel transistor .[.(M7).]. for receiving the reverse selection signal .[.(Sij*).].. 
     
     
       4. A crosspoint according to claim 1, wherein each of said columns comprises, in series with a resistor .[.(R).]., a bipolar transistor .[.(Q).]., the collector of which is connected to said resistor, the emitter of which is connected to one of said pair of conductors of said column, and the base of which is connected to a high voltage supply source. 
     
     
       5. A crosspoint according to claim 1, wherein said first differential amplifier comprises, in parallel, two legs respectively comprising a first P-channel transistor .[.(M5).]. and a first N-channel transistor .[.(M3).]., and a second P-channel transistor .[.(M6).]. and a second N-channel transistor .[.(M4).]., the drains of said P-channel transistors being connected to said high voltage source and the sources of said N-channel transistors being connected to a low voltage supply terminal .[.(Vss).]. through a third N-channel transistor .[.(M7).].. 
     
     
       6. A crosspoint according to claim 5, herein said means for setting the voltage comprises a fifth N-channel transistor .[.(M8).]. connected in parallel to said third N-channel transistor and receiving the reverse selection signal .[.(Sij*).].. 
     
     
       7. A crosspoint according to claim 5, wherein said first current source comprises a third P-channel transistor .[.(M11).]., the drain of which is connected to the gate thereof, a sixth N-channel transistor .[.(M10).]., the gate of which receives a selection signal .[.(Sij).]. of said crosspoint, and a seventh N-channel transistor .[.(M9).]., the drain of which is connected to the gate thereof, said current mirror circuit being implemented by the gate interconnection of said first, second and third N-channel transistors, the gates of said first and second N-channel transistors being connected respectively to each input conductor and the gates of said first and second N-channel transistors being connected respectively to the control gates of said second differential amplifier. .Iadd. 
     
     
       8.  A switching matrix crosspoint circuit, comprising: a plurality of differential input signal connections,   a plurality of differential output signal connections, and   a plurality of selectable switch elements each having a differential input operatively connected to a particular respective one of said differential input signal connections and having a differential output operatively connected to a particular respective one of said output signal connections;   individual ones of said switch elements each being connected to receive a respective selection signal, and comprising at least one pair of field-effect input transistors having respective gates connected to receive respective portions of said input signal,   current-generation circuitry connected to pass a substantially constant current through said input transistors when said selection signal is active, and   disabling circuitry connected to bias said input transistors so that said input transistors effectively hold both sides of said differential output off, when said selection signal is inactive. .Iaddend..Iadd.9. The circuit of claim 8, wherein each said differential output signal connection is connected to a positive supply voltage through a pair of load elements.     
     
     
        .Iaddend..Iadd.10.  The circuit of claim 8, wherein said input transistors are N-channel field-effect transistors, and said disabling circuitry is connected to selectively pull down the sources of said input transistors, and said input transistors have drains thereof connected to drive gates of an additional pair of N-channel field-effect transistors, and said additional pair of N-channel field-effect transistors are operatively connected to drive said differential output signal connections. .Iadd.11. The circuit of claim 8, wherein said input transistors are N-channel field-effect transistors. .Iaddend..Iadd.12. The circuit of claim 8, wherein said current-generation circuitry includes at least two current 
     
     
        mirrors. .Iaddend..Iadd.13.  A switching matrix crosspoint circuit, comprising: a plurality of differential input signal connections,   a plurality of differential output signal connections,   a plurality of switch elements each having a differential input operatively connected to a particular respective one of said differential input signal connections, and each having a differential output operatively connected to a particular respective one of said output signal connections, and each being connected to receive a respective selection signal, and each comprising at least one pair of field-effect input transistors having respective gates connected to receive respective portions of said input signal,   an additional pair of transistors connected to be driven by said pair of input transistors,   disabling circuitry connected to bias said input transistors so that said additional transistors are turned off, whenever said selection signal is inactive;   wherein multiple ones of said additional pairs of transistors each have first current-carrying terminals thereof differentially connected to a common one of said differential outputs, and have second current-carrying terminals thereof connected in common to a single shared current sink. .Iaddend..Iadd.14. The circuit of claim 13, wherein each said differential output signal connection is connected to a positive supply voltage through     
     
     
        a pair of load elements. .Iaddend..Iadd.15.  The circuit of claim 13, wherein said input and additional transistors are all N-channel field-effect transistors. .Iaddend..Iadd.16. The circuit of claim 13, wherein said input transistors are N-channel field-effect transistors, and said disabling circuitry is connected to selectively pull down the sources of said input transistors. .Iaddend..Iadd.17. A switching matrix crosspoint circuit, comprising: a plurality of differential input signal connections,   a plurality of differential output signal connections, and   a plurality of selectable switch elements each having a differential input operatively connected to a particular respective one of said differential input signal connections and having a differential output operatively connected to a particular respective one of said output signal connections;   each said switch element comprising at least two differential amplifier stages cascaded together. .Iaddend..Iadd.18. The circuit of claim 17, further comprising a respective complementary pair of control lines connected to operate each of said switch elements. .Iaddend..Iadd.19. The circuit of claim 17, wherein each said differential output signal connection is connected to a positive supply voltage through a pair of   
     
     
        load elements. .Iaddend..Iadd.20.  The circuit of claim 17, wherein each said differential amplifier stage includes a balanced pair of N-channel field-effect transistors having gates connected to receive inputs. .Iaddend..Iadd.21. A switching matrix crosspoint circuit, comprising: a plurality of differential input signal connections,   a plurality of output signal connections, and   a plurality of selectable switch elements each having a differential input connected to a particular respective one of said differential input signal connections and having an output connected to a particular respective one of said output signal connections;   each said switch element comprising at least one amplifier and also at least one level shifter circuit portion. .Iaddend..Iadd.22. The circuit of claim 21, further comprising a respective complementary pair of control lines connected to operate each of said switch elements. .Iaddend..Iadd.23. The circuit of claim 21, wherein said amplifier and said level shifter portion both include N-channel field-effect transistors. .Iaddend..Iadd.24. The circuit of claim 21, wherein each said output signal connection is a differential connection. .Iaddend..Iadd.25. The circuit of claim 21, wherein each said output signal connection is connected to a positive supply voltage through a load element. .Iaddend.