Semiconductor memory device having a test mode setting circuit

Abstract

In a semiconductor memory device having a test mode setting circuit, when a voltage higher than a common operation range is applied to an input terminal (101) receiving CAS signals, a first voltage detecting circuit (100) detects the voltage and the detected output is latched in a latch circuit (110). A voltage setting circuit . .(1 20).!. .Iadd.(120) .Iaddend.sets a cell plate voltage of a memory cell . .(1a).!. .Iadd.(1) .Iaddend.approximately at the ground potential in response to the latch output. Consequently, the operation margin of the memory cell for the data "1" can be carried out by the V bump test. Meanwhile, when a voltage higher than the normal operation range is applied to an input terminal (201) receiving WE signals, a second voltage detecting circuit (200) detects the voltage and the detected output is latched in the latch circuit . .(201).!..Iadd.(210).Iaddend.. The voltage setting circuit sets the cell plate voltage approximately at Vcc in response to the latch output from the latch circuit.

What is claimed is: . .1. A semiconductor memory device having a test mode setting circuit, comprising: 
     
        generated by said constant voltage generating means..!.2. A semiconductor memory device having a test mode setting circuit . .according to claim 1.!., .Iadd.comprising: a plurality of memory cells each formed of an insulating gate type field effect transistor and a capacitance;   external input means to which a control signal is externally applied;   constant voltage generating means connected to one electrode of said capacitance; and   control means for controlling, when a signal voltage applied to said external input means is out of a predetermined operation range, a voltage generated by said constant voltage generating means, .Iaddend.wherein   said input means includes two external input terminals and said control means comprises   first voltage detecting means detecting that a signal voltage applied to one of said external input terminals becomes higher than a predetermined voltage,   second voltage detecting means detecting that a signal voltage applied to the other of said external input terminals becomes higher than a predetermined voltage, and   voltage setting means outputting a reference voltage potential from said constant voltage generating means in response to a detection output of said first voltage detecting means, and outputting a voltage at a nominal supply potential in response to a detection output from said second   
     
     
        voltage detecting means. 3. A semiconductor memory device having a test mode setting circuit according to claim 2, wherein said voltage setting means comprises   first latch means latching an output of said first voltage detecting means, and   second latch means latching an output of said second voltage detecting   
     
     
        means. 4. A semiconductor memory device having a test mode setting circuit according to claim 3, wherein said first and second latch means comprise means for releasing latch when   
     
     
        power supply is cut off. 5. A semiconductor memory device having a test mode setting circuit according to claim 2, wherein said first and second voltage detecting means respectively comprise a   
     
     
        plurality of field effect transistors connected in series. 6. In a semiconductor memory device including a plurality of memory cells each formed of an insulating gate type field effect transistor and a capacitor, a test mode setting and control circuit comprising: first voltage detection means for generating a first output signal in response to a firm control voltage exceeding a first predetermined level, and   second voltage detection means for generating a second output signal in response to a second control voltage exceeding a second predetermined level,   voltage setting means for applying a cell plate voltage to a memory cell capacitor in response to either said first output signal or said second output signal,   said voltage setting means comprising: a) means responsive to said first output signal for applying a cell plate voltage to said memory cell capacitor having a value which is approximately twice the value of the cell plate voltage applied during normal memory operation, and   b) means responsive to said second output signal for applying a cell plate     
     
     
        voltage of a reference potential to said memory cell capacitor. 7. A method of testing a semiconductor memory device including a plurality of control terminals for controlling normal memory operation and a plurality of memory cells each formed of an insulating gate type field effect transistor and a capacitor, said method comprising the steps of: applying a test control signal to a first terminal of said control terminals for testing a first data level,   applying a test control signal to a second terminal of said control terminals for testing a second data level,   detecting a voltage at said first and second terminals,   generating a first output signal in response to a detected voltage level at said first terminal exceeding a first predetermined normal operating level,   generating a second output signal in response to a detected voltage level at said second terminal exceeding a second predetermined normal operating level,   applying a cell plate voltage to said memory cell capacitor having a value which is approximately twice the value of the cell plate voltage applied during normal memory operation in response to said first output signal, and   applying a cell plate voltage of a reference potential to said memory cell capacitor in response to said second output signal. . .8. A semiconductor memory device having a test mode setting circuit for supply voltage fluctuation tests, comprising:   a plurality of memory cells, each of which comprising a field effect transistor and a capacitor;   a constant voltage generating means connected to one electrode of the capacitor for applying a bias voltage to the capacitor for reducing the electrical field in the capacitor during normal operation;   an external input terminal for receiving control signals during normal operation; and   control means for varying the bias voltage to the capacitor in response to application of a signal voltage outside an operating range of the control   
     
     
        signals to the external input terminal..!..Iadd.9.  For a semiconductor memory device comprising a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell; a test voltage generating circuit for margin testing said memory cell, comprising a cell plate voltage modifying circuit coupled to said intermediate potential generating means and including a first transistor connected between a supply potential node to which the supply potential is applied and said output node, and a second transistor connected between a ground potential node to which ground potential is applied and said output node, said first and second transistors being rendered non-conductive in normal operation for outputting the intermediate potential from said intermediate potential generating means to the output node, said first transistor being rendered conductive and said second transistor rendered non-conductive in a first test period of a test mode for outputting a potential higher than the intermediate potential from said intermediate potential generating means to said output node, and said first transistor being rendered non-conductive and said second transistor being rendered conductive in a second test period of the test mode for outputting a potential lower than the intermediate potential from said intermediate potential generating means to said output node..Iaddend..Iadd.10. For a semiconductor memory device comprising a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell;   a test voltage generating circuit for margin testing said memory cell, comprising a cell plate voltage modifying circuit coupled to said intermediate potential generating means and including a first transistor connected between said output node and a supply potential node, receiving a first potential higher than the intermediate potential provided from said intermediate potential generating means in normal operation in data writing in a test mode and receiving a second potential higher than the first potential in data reading in the test mode, and a second transistor connected between a ground potential node to which ground potential is applied and said output node, said first and second transistors being rendered non-conductive in normal operation for outputting the intermediate potential from said intermediate potential generating means to the output node, said first transistor being rendered conductive and said second transistor being rendered non-conductive in the test mode for outputting the potential applied to said supply potential node to said output node..Iaddend..Iadd.11. For a semiconductor memory device comprising a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell;   a test voltage generating circuit for margin testing said memory cell, comprising a cell plate voltage modifying circuit coupled to said intermediate potential generating means, wherein   said intermediate potential is applied to said output node in normal operation, a first supply potential is applied to the output node when data is written to said memory cell in a test mode, and a second supply potential higher than the first supply potential is applied to the output node when data is read from said memory cell in the test mode..Iaddend..Iadd.12. For a semiconductor memory device comprising a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell;   a test voltage generating circuit for margin testing said memory cell, comprising a cell plate voltage modifying circuit coupled to said intermediate potential generating means, wherein   a first supply potential is applied to the output node when data is written to said memory cell in a first test period of a test mode, a second supply potential higher than the first supply potential is applied to the output node when data is read from said memory cell in the first test period of the test mode, and ground potential is applied to the output node when data is read from said memory cell in a second test period of the test mode..Iaddend..Iadd.13. For a semiconductor memory device comprising a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell, said intermediate potential generating means including a first resistive element connected between a supply potential node to which the supply potential is applied and said output node and a second resistive element connected between said output node and a ground potential node to which ground potential is applied;   a test voltage generating circuit for margin testing said memory cell, comprising a cell plate voltage modifying circuit coupled to said intermediate potential generating means and including a first transistor connected between the supply potential node and said output node, and a second transistor connected between the ground potential node and said output node, wherein   said first and second transistors are rendered non-conductive in normal operation and either said first transistor or said second transistor is rendered conductive in a test mode..Iaddend..Iadd.14. For a semiconductor memory device comprising a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell;   a test voltage generating circuit for margin testing said memory cell, comprising a cell plate voltage modifying circuit coupled to said intermediate potential generating means and including a first transistor connected between said output node and a supply potential node to which a first potential higher than the intermediate potential from said intermediate potential generating means is applied in normal operation, said first potential is applied in data writing at a test mode and a second potential, higher than said first potential, is applied in data reading at the test mode, and a second transistor connected between said output node and a ground potential node to which ground potential is applied, wherein   said first and second transistors are rendered non-conductive in normal operation for outputting the intermediate potential from said intermediate potential generating means to the output node, and said first transistor is rendered conductive and said second transistor rendered non-conductive in the first test for outputting the potential applied to said supply potential node to said output node..Iaddend..Iadd.15. For a semiconductor memory device comprising a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell;   a test voltage generating circuit for margin testing said memory cell, comprising a cell plate voltage modifying circuit coupled to said intermediate potential generating means and including a first transistor connected between said output node and a supply potential node to which a first potential is applied in data writing at a test mode and a second potential, higher than said first potential, is applied in data reading at the test mode, and a second transistor connected between said output node and a ground potential node to which ground potential is applied, wherein   said first and second transistors are rendered non-conductive in normal operation for outputting the intermediate potential from said intermediate potential generating means to the output node, said first transistor is rendered conductive and said second transistor rendered non-conductive in a first test period of the test mode for applying the potential applied to said supply potential node to said output node, and said first transistor is rendered non-conductive and said second transistor is rendered conductive in a second test period of the test mode for outputting a potential lower than the intermediate potential from said intermediate potential generating means to said output node..Iaddend..Iadd.16. For a semiconductor memory device comprising   a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor,   an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell, and   a test voltage generating circuit for margin testing said memory cell, said test voltage generating circuit including a cell plate voltage modifying circuit coupled to said intermediate potential generating means and having a first transistor connected between a supply potential node to which the supply potential is applied and said output node, and a second transistor connected between a ground potential node to which ground potential is applied and said output node,     a method of margin testing said memory cell, comprising the steps of:   applying, in a first test period of a test mode, a potential higher than the intermediate potential applied in the normal operation to the other electrode of the capacitor of said memory cell; and   applying, in a second test period of a test mode, a potential lower than the intermediate potential applied in said normal operation to the other electrode of the capacitor of said memory cell..Iaddend..Iadd.17. For a semiconductor memory device comprising   a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor,   an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell, and   a test voltage generating circuit for margin testing said memory cell, said test voltage generating circuit including a cell plate voltage modifying circuit coupled to said intermediate potential generating means and having a first transistor connected between a supply potential node to which the supply potential is applied and said output node, and a second transistor connected between a ground potential node to which ground potential is applied and said output node,     a method of margin testing said memory cell, comprising the steps of:   applying a first potential higher than the intermediate potential applied in the normal operation to the other electrode of the capacitor of said memory cell in data writing at a test mode, and   applying a second potential higher than said first potential to the other electrode of the capacitor of said memory cell in data reading at the test   
     
     
        mode..Iaddend..Iadd.18.  The method according to claim 17, wherein said first potential is the same as the supply potential applied in the data writing at the test mode..Iaddend..Iadd.19. For a semiconductor memory device comprising   a memory cell having an insulated gate type field effect transistor having one main electrode connected to a corresponding bit line and its gate electrode connected to a corresponding word line, and a memory cell capacitor having one electrode connected to the other main electrode of the insulated gate type field effect transistor,   an intermediate potential generating means for applying an intermediate potential between ground potential and a supply potential applied in normal operation to an output node connected to the other electrode of the capacitor of said memory cell, and   a test voltage generating circuit for margin testing said memory cell, said test voltage generating circuit including a cell plate voltage modifying circuit coupled to said intermediate potential generating means and having a first transistor connected between a supply potential node to which the supply potential is applied and said output node, and a second transistor connected between a ground potential node to which ground potential is applied and said output node,     a method of margin testing said memory cell, comprising the steps of:   applying, when data is written to said memory cell in a first period of a test mode, the same potential as the power supply potential to the other electrode of the capacitor of said memory cell;   applying, when data is read from said memory cell in the first period of the test mode, a potential higher than the potential applied when data is written to said memory cell in a first period of the test mode operation to the other electrode of the capacitor of said memory cell; and   applying, when data is written and data is read in a second period of the test mode, a potential lower than the intermediate potential to the other electrode of the capacitor in said memory cell..Iaddend.