Dynamic video RAM incorporating on chip vector/image mode line modification

Abstract

An architecture for a dynamic video random access memory on a single integrated circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information in the RAM and further having the write masking circuitry for modifying selected portions of the line of stored video information between selected START and STOP bit locations within the line.

I claim: 
     
       1. An architecture for addressing and modifying vectors in a dynamic video random access memory placed on an integrated circuit chip, said dynamic video random access memory being connected to a bus (90, 100), said bus delivering vector addresses, source data, drawing rules and START and STOP locations, said source data being new data to be used to modify an addressed vector, said START and STOP locations defining the portion of said addressed vector to be modified, and said drawing rule being the logical operation combining said source data with said data portion between said START and STOP locations of said addressed vector, said architecture on said integrated circuit chip comprising: a memory (1300) for storing vectors of video information, said memory having a plurality of "n"×"m" bit pages (PG), each of said pages having defined page column (PC) and page row (PR) locations in said memory, each said page containing a plurality of horizontal (610) and vertical (600) vectors, each said horizontal vector being defined by a vector row location in said page and each said vertical vector being defined by a vector column in said page,   address means (1360) connected to said bus for receiving the address of a horizontal or vertical vector in a page of said memory to be modified, said address comprising: (a) a first plurality of bits for defining the page row of said addressed page,   (b) a second plurality of bits for defining the page column of said addressed page, and   (c) a third plurality of bits for defining the addressed vector in said addressed page,     data means (1340) connected to said bus for receiving said source data, and   control means (1366, 1360, 1354, 1336) connected to said memory, said address means, and said data means for modifying the stored video information with said source data at the addressed vector in said memory wherein said data means further receives said drawing rule from said bus, said drawing rule being used by said control means to modify said line of stored video information between said START and STOP locations.   
     
     
       2. The architecture of claim 1 wherein said third plurality of bits includes at least one bit for defining whether the addressed vector is horizontal or vertical. 
     
     
       3. The architecture of claim 1 wherein said memory has at least 32 by 32 bit pages. 
     
     
       4. The architecture of claim 1 wherein said memory comprises a plurality of memory blocks of at least 160 memory cells by 1024 memory cells. 
     
     
       5. The architecture of claim 1 wherein said control means utilizes a single clock input to said integrated circuit chip for performance of said modification. 
     
     
       6. The architecture of claim 1 wherein said architecture is capable of modifying at least three million vectors per second. 
     
     
       7. The architecture of claim 1 further comprising means (1360) connected to said memory for delivering said vector of stored video information from said memory based upon said addressed vector from said address means. 
     
     
       8. The architecture of claim 1 further comprising: drawing rule means (1354) receiving said line of stored video information and connected to said data means for obtaining said drawing rule, said drawing rule means logically combining said line of stored video information and said source data according to said drawing rule logical operation to modify said line of stored video information,   write mask means (1336) connected to said data means for obtaining said START and STOP locations and connected to said memory for allowing said writing of said logical combination only between said START and STOP bit locations of said line, and   said control means activating said drawing rule means to perform said logical combination, and said control means then writing said modified line of video information resulting from said logical combination into said memory only between said START and STOP bit locations.   
     
     
       9. The architecture of claim 1 wherein said bus comprises an address bus (100) and a data bus (90). 
     
     
       10. An architecture for addressing and modifying vectors in a dynamic video random access memory placed on a single integrated circuit chip, said dynamic video random access memory being connected to a bus (90, 100); said bus delivering vector addresses, source data, drawing rules and START and STOP locations, said source data being new data to be used to modify an addressed vector, said START and STOP locations defining the portion of said addressed vector to be modified, and said drawing rule being the logical operation combining said source data with said data portion between said START and STOP location of said addressed vector, said architecture on said integrated circuit chip comprising: a memory (1300) for storing vectors of video information,   address means (1360) connected to said bus for receiving the address of a vector in said memory to be modified,   data means (1340) connected to said bus for receiving said source data for modifying the stored video information at said addressed vector, and   control means (1366, 1360, 1354, 1336) connected to said memory, said address means, and said data means for modifying the stored video information with said source data at the addressed vector location in said memory wherein said data means further receives a drawing rule from said bus, said drawing rule being used by said control means to modify said addressed vector of stored video information, said data means further receiving the START and STOP locations for said modification of said addressed vector of stored video information between said START and STOP locations.   
     
     
       11. The architecture of claim 10 wherein said control means utilizes a single clock input to said chip for performance of said modification. 
     
     
       12. The architecture of claim 10 wherein said architecture is capable of modifying at least three million vectors per second. 
     
     
       13. The architecture of claim 10 further comprising: drawing rule means (1354) receiving said addressed vector of stored video information and connected to said data means for obtaining said drawing rule, said drawing rule means logically combining said addressed vector of stored video information and said source data according to said drawing rule logical operation to modify said addressed vector of stored video information,   write mask means (1336) connected to said data means for obtaining said START and STOP locations and connected to said memory for allowing said writing of said logical combination only between said START and STOP bit locations of said addressed vector, and   said control means activating said drawing rule means to perform said logical combination, and said control means then writing said modified line of video information resulting from said logical combination into said memory only between said START and STOP bit locations.   
     
     
       14. The architecture of claim 10 wherein said bus comprises an address bus (100) and a data bus (90). 
     
     
       15. An architecture for addressing a dynamic video random access memory with both image and vector addresses, said dynamic video random access memory being connected to a bus (90, 100), said bus providing said image and vector addresses and source data, said source data for modifying the stored video information at said vector and image addresses, said architecture comprising: a memory (1300) for storing video information, said memory being addressed with said vector and image addresses, said memory: (a) when addressed with said vector addresses, having a plurality of pages (PG), each of said pages having defined page column (PC) and page row (PR) locations in said memory, each said page containing a plurality of horizontal (610) and vertical (600) vectors, each said horizontal vector being defined by a vector row location in said page and each said vertical vector being defined by a vector column in said page,   (b) when addressed with said image addresses, having a plurality of scan lines, each of said scan lines containing a plurality of words,     address means (1360) connected to said bus for receiving an address mode (V/I), and either the vector address for a horizontal or vertical vector to be modified in said memory or the image address of a word to be modified in said memory,   said vector address comprising: (a) a first plurality of bits for defining the page row of said addressed page,   (b) a second plurality of bits for defining the page column of said addressed page, and   (c) a third plurality of bits for defining the page addressed vector in said addressed page,     said image address comprising: (a) a first plurality of bits for defining the scan line being addressed, and   (b) a second plurality of bits for defining the addressed word in said addressed scan line,     data means (1340) connected to said bus for receiving said source data, and   control means (1366, 1360, 1354, 1336) connected to said memory, said address means, and said data means for addressing said memory with said address in said address means to modify the stored video information with said source data in said data means.   
     
     
       16. The architecture of claim 15 wherein said memory, said address means, said data means, and said control means reside on a single integrated circuit chip. 
     
     
       17. The architecture of claim 16 wherein said control means utilizes a single clock input to said chip for performance of said modification. 
     
     
       18. The architecture of claim 15 wherein said data means further receives a drawing rule from said bus, said drawing rule being the logical operation for modifying said addressed vector of stored video information, said data means further receiving the START and STOP locations for modifying said addressed vector of stored video information, said START and STOP locations being the beginning and ending bit locations in said addressed vector between which said modification of said line occurs. 
     
     
       19. The architecture of claim 18 further comprising: drawing rule means (1354) receiving said addressed vector of stored video information and connected to said data means for obtaining said drawing rule, said drawing rule means logically combining said addressed vector of stored video information and said source data according to said drawing rule logical operation to modify said addressed vector of stored video information,   write mask means (1336) connected to said data means for obtaining said START and STOP locations and connected to said memory for allowing said writing of said logical combination only between said START and STOP bit locations of said addressed vector, and   said control means activating said drawing rule means to perform said logical combination, and said control means then writing said modified line of video information resulting from said logical combination into said memory only between said START and STOP bit locations.   
     
     
       20. The architecture of claim 15 wherein said third plurality of bits in said vector address includes at least one bit for defining whether the addressed vector is horizontal or vertical. 
     
     
       21. The architecture of claim 15 wherein said memory in the vector mode has at least 32 by 32 bit pages. 
     
     
       22. The architecture of claim 15 wherein said memory comprises a plurality of memory blocks of at least 160 memory cells by 1024 memory cells. 
     
     
       23. The architecture of claim 15 wherein said architecture is capable of modifying at least three million vectors per second. 
     
     
       24. The architecture of claim 15 wherein said bus comprises an address bus (100) and a data bus (90). 
     
     
       25. An architecture for addressing a dynamic video random access memory with both image and vector addresses, said dynamic video random access memory being connected to a bus (90, 100), said bus providing said image and vector address and source data, said source data for modifying the stored video information at said vector and image addresses, said architecture comprising: a memory (1300) for storing video information, said memory being addressed with said vector and image addresses, said memory: (a) when addressed with said vector addresses, having a plurality of pages (PG), each said page containing a plurality of vectors,   (b) when addressed with said image addresses, having a plurality of scan lines, each of said scan lines containing a plurality of words,     address means (1360) connected to said bus for receiving an address mode (V/I), and either the vector address for a vector to be modified in said memory or the image address of a word to be modified in said memory,   said vector address comprising: (a) a first plurality of bits for defining said addressed page, and   (b) a second plurality of bits for defining the addressed vector in said addressed page,     said image address comprising: (a) a first plurality of bits for defining the scan line being addressed, and   (b) a second plurality of bits for defining the addressed word in said addressed scan line,     data means (1340) connected to said bus for receiving said source data, and   control means (1366, 1360, 1354, 1336) connected to said memory, said address means, and said data means for addressing said memory with said address in said address means to modify the stored video information with said source data in said data means.   
     
     
       26. An architecture for addressing with both image and vector addresses a dynamic video random access memory, said dynamic video random access memory being connected to a bus (90, 100), said bus providing said image and vector address and source data, said source data for modifying the stored video information at said vector and image addresses, said architecture comprising: a memory (1300) for storing video information; said memory being addressed with said vector address or with said image address; said memory, in the vector address mode, having a plurality of pages (PG) each of said pages containing a plurality of vectors; said memory, in the image address mode having a plurality of scan lines; each of said scan lines containing a plurality of words,   address means (1360) connected to said address bus for receiving said vector address of a vector to be modified in said memory or said image address of a word to be modified in said memory; said vector address defining (a) said addressed page and (b) the addressed vector in said addressed page; said image address defining (a) the scan line being addressed and (b) the word in said addressed scan line,   data means (1340) connected to said bus for receiving said source data for modifying the stored video information at said vector or image address, and   control means (1366, 1360, 1354, 1336) connected to said memory, said address means, and said data means for addressing said memory with said address in said address means to modify the stored video information with said source data.   
     
     
       27. The architecture of claim 26 wherein said vector mode can be addressed by horizontal or vertical vectors. 
     
     
       28. The architecture of claim 26 wherein said control means utilizes a single clock input to said chip for the performance of said modification. 
     
     
       29. The architecture of claim 26 wherein said architecture is capable of modifying at least three million vectors per second. 
     
     
       30. The architecture of claim 26 wherein said bus comprises an address bus (100) and a data bus (90). 
     
     
       31. The architecture of claim 26 wherein said memory, said address, said data means and said control means reside on a single integrated circuit chip. 
     
     
       32. A dynamic video RAM connected to a random bus and to a serial bus, said RAM comprising: a single integrated circuit chip (10) connected to said serial and random buses,   a memory (1300) on said chip for storing video information, said memory being addressed in serial data transfer, vector, and image modes of operation, said memory: (a) in said vector address mode, having a plurality of pages (PG), each said page containing a plurality of horizontal (610) and vertical (600) vectors,   (b) in said image address mode, having a plurality of scan lines, each of said scan lines containing a plurality of scan words,   (c) in said serial data transfer mode, having a plurality of partial scan lines, each of said partial scan lines containing a plurality of partial scan words,     address means (1360) on said chip and connected to said random bus for receiving the mode of operation and (1) the vector mode address for a vector in said memory, (2) the image mode address for a scan line in said memory, or (3) the serial data transfer address for the partial scan line in said memory,   random control means (1366, 1360, 1354, 1336, 1340) connected to said memory and said address means for accessing information at the memory locations of said image mode or vector mode addresses, said random control means reading said memory at said serial data transfer addresses, and   serial port control means (1304, 1306, 1314) connected to said memory for delivering said read information at said serial data transfer address to said serial bus.   
     
     
       33. The RAM of claim 32 wherein said random port control means receives over the random bus (1) a vector/image (V/I) signal for determining the vector or image addressing mode of operation, (2) a read/write (R/W) signal for determining whether to read or write said memory, and (3) a clock signal (RCLK) for performing all random port operations of said dynamic video RAM. 
     
     
       34. The architecture of claim 32 wherein said random port control means is a random state machine. .Iadd. 
     
     
       35.  A system comprising a memory, a circuit for accessing said memory, and a bus connecting said circuit to said memory, said circuit comprising means for providing a first address and a second address on said bus, said first address being valid on said bus on a first edge of a clock signal and said second address being valid on said bus on a second edge of said clock signal, said first edge of said clock signal being different from said second edge of said clock signal; and   said memory being a synchronous dynamic random access memory integrated circuit comprising: a memory block including a plurality of memory cells for storing information;   an input for receiving said clock signal;   address input means for receiving and holding said first address from said bus in response to said first edge of said clock signal, and for receiving and holding said second address from said bus in response to said second edge of said clock signal; and   access means for accessing a location in said memory block corresponding to said first address and said second address held by said address input means. .Iaddend..Iadd.36. The system of claim 35, wherein said access means comprises:     output means for outputting, to said bus, information stored at said location of said memory block in response to a third edge of said clock signal. .Iaddend..Iadd.37. The system of claim 36,   said circuit for accessing further comprising: means for providing on said bus a control input, said control input being valid on an edge of said clock signal,     said memory further comprising: control means for supplying a first enable signal and a second enable signal to said address input means in response to said control input on an edge of said clock signal, and for supplying an output enable signal to said output means in response to said control input on an edge of said clock signal, each of said first enable signal, said second enable signal and said output enable signal being synchronous with an edge of said clock signal, and     wherein said address input means holds said first address based on said first enable signal, said address input means holds said second address based on said second enable signal, and said output means outputs said information based on said output enable signal. .Iaddend..Iadd.38. The system of claim 35,   said circuit for accessing further comprising: means for providing data on said bus which is valid on a third edge of said clock signal,     wherein said access means comprises: data input means for receiving said data from said bus, said data input means holding said data in response to said third edge of said clock signal; and   write means for writing said data to said memory block at said location corresponding to said first address and said second address in response to a fourth edge of said clock signal. .Iaddend..Iadd.39. The system of claim 38,     said circuit for accessing further comprising: means for providing on said bus a control input, said control input being valid on an edge of said clock signal;     said memory further comprising: control means for supplying a data enable signal to said data input means in response to said control input on an edge of said clock signal, and for supplying a write enable signal to said write means in response to said control input on an edge of said clock signal, each of said data enable signal and said write enable signal being synchronous with an edge of said clock signal, and   wherein said data input means provides said data to said write means in response to said data enable signal. .Iaddend..Iadd.40. The system of claim 35,     wherein said bus includes an address bus for conveying said first address and said second address and a data bus for conveying said data. .Iaddend..Iadd.41. The system of claim 35, wherein said clock signal has a frequency of about 16.7 MHZ. .Iaddend..Iadd.42. The system of claim 35, wherein:   said bus comprises a first bus on which said first address and said second address are provided and which also conveys data between said circuit and said memory, and a second bus connecting said circuit to said memory for conveying a control input defining an operation mode;   said circuit further comprises means for providing said control input on said second bus, and means for providing access information defining a specification of said operation mode on said first bus, said access information being valid on said first bus on a third edge of said clock signal, and said control input being valid on said second bus on an edge of said clock signal; and   said memory further comprises: access information input means for receiving said access information through said first bus, said access information input means providing said access information as an output in response to said third edge of said clock signal; and   control means for receiving said control input through said second bus, and for controlling operations of said address input means, said access information input means and said access means in response to said control input on an edge of said clock signal. .Iaddend..Iadd.43. The system of claim 35, wherein:     said circuit further comprises means for providing a control input on said bus, said control input being valid on said bus on an edge of said clock signal; and   said memory operates by use of edges of said clock signal and further comprises control means for receiving said control input indicating a read/write mode defining one of a read mode and a write mode, and for changing said read/write mode based on a difference of level of said control input at two successive edges of said edges of said clock signal. .Iaddend..Iadd.44. The system of claim 43, wherein:   said first address held by said address input means is maintained before and after a level change of said control input resulting in said difference of level. .Iaddend..Iadd.45. The system of claim 35, wherein:   said circuit further comprises means for providing a control input on said bus, said control input being valid on said bus on an edge of said clock signal; and   said memory further comprising control means for outputting an internal control signal defining a timing of an internal operation of said synchronous dynamic random access memory based on a control input on an edge of said clock signal;   wherein said control means generates new state information in accordance with a control input and state information output in response to a third edge of said clock signal, and outputs a new internal control signal based on said new state information in response to a fourth edge of said clock signal, said third edge of said clock signal being different from said   
     
     
        fourth edge of said clock signal. .Iaddend..Iadd.46.  The system of claim 45, wherein: said internal control signal is a precharge control signal provided to said memory block. .Iaddend..Iadd.47. The system of claim 35, wherein:   said memory block comprises a plurality of individual memory blocks and said access means further comprises output means for sequentially outputting a plurality of data which belong to separately addressable locations in said individual memory blocks at substantially a same interval, said plurality of data including data stored at a location in said memory block corresponding to said first address and said second address. .Iaddend..Iadd.48. The system of claim 35, wherein:   said circuit further comprises means for providing a control input on said bus, said control input being valid on said bus on an edge of said clock signal; and   said memory comprises a random state machine. .Iaddend..Iadd.49. The system of claim 48, wherein:   said random state machine determines a new state based on said control input and a current state, and outputs an internal control signal based on said new state in response to an edge of said clock signal, said internal control signal defining a timing of an internal operation of said memory. .Iaddend..Iadd.50. The system of claim 49, wherein:   said random state machine comprises decoding means for decoding said new state so as to output said internal control signal. .Iaddend..Iadd.51. The system of claim 35, said memory further comprising:   control means for receiving a predetermined set of control signals provided from outside of said memory, for transitioning from one state to at least one next state in accordance with said predetermined set of control signals on respective edges of said clock signal, and for outputting internal control signals defining timings of internal operations of said memory based on the at least one next state;   wherein said predetermined set of control signals include a first control signal and a second control signal, said internal operations represent a write operation when said first control signal is active and said second control signal is active, and said internal operations represent a read operation when said first control signal is inactive and said second   
     
     
        control signal is active. .Iaddend..Iadd.52.  The system of claim 51, wherein a level of said first control signal is changed during a period when said second control signal is active, and said operation of said memory is changed between said read operation and said write operation in accordance with said level change of said first control signal without the control means reverting back to a state prior to starting either said read operation or said write operation. .Iaddend..Iadd.53. The system of claim 45, wherein said state information may be any one of a first state information indicating an initial state and a plurality of second state information indicating respective states other than said initial state, and with respect to at least one of the plurality of second state information when said state information output in response to said third edge of said clock signal is said at least one second state information, said new state information may be any one of a predefined plurality of second state information from among said plurality of second state information, each of said predefined plurality of second state information indicating respective states other than said initial state. 
     
     
        .Iaddend..Iadd.4.  The system of claim 49, wherein said current state and said new state may be any one of a first state indicating an initial state and a plurality of second states each indicating a state other than said initial state, and with respect to at least one of the plurality of second states when said current state is said at least one second state, said new state may be any one of a predefined plurality of second states from among said plurality of second states, each of said predefined plurality of second states indicating states other than said initial state. .Iaddend.