Logic array having high frequency internal clocking

Abstract

A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.

What is claimed is: 
     
       1. A state machine structure comprising: logic array means having input leads and output leads;   at least one register means having input terminals coupled to said output leads of said logic array means and having output terminals coupled to said input leads of said logic array means; and   clock generating means for generating a clock signal having a frequency different than a reference signal applied to said clock generating means, said clock generating means having an output coupled to a clock input terminal of one or more of said register means; wherein said clock generating means incorporates a phase-locked loop having first and second inputs, and having said reference signal coupled to said first input of said phase-locked loop, and an output terminal of said register means coupled to said second input of said phase-locked loop.   
     
     
       2. The structure of claim 1 wherein said structure is a monolithic structure. 
     
     
       3. The structure of claim 2 wherein said coupling between said output terminal of said register means and said second input of said phase-locked loop is accomplished through a connection external to said monolithic structure. 
     
     
       4. The structure of claim 2 wherein said logic array means comprises an AND array means having input leads and output leads, an OR array means having input leads coupled to said output leads of said AND array means and having output leads, said register means having input terminals coupled to said output leads of said AND array means, but not coupled to said output leads of said OR array, and having output terminals coupled to said input leads of said AND array means. 
     
     
       5. The structure of claim 2 wherein said coupling between said output terminal of said register means and said second input of said phase-locked loop is accomplished through a connection internal to said monolithic structure. 
     
     
       6. The structure of claim 2 wherein said reference signal is an externally generated clock signal. 
     
     
       7. The structure of claim 2 wherein said logic array means comprises: AND array means for performing functional AND operations having input leads and output leads; and   OR array means for performing functional OR operations having input leads coupled to said output leads of said AND array means and having output leads.   
     
     
       8. The structure of claim 7 wherein said AND array means is programmable. 
     
     
       9. The structure of claim 7 wherein at least one of said register means comprises output register means having input terminals coupled to said output leads of said OR array means and having output terminals coupled to output leads of said structure. 
     
     
       10. The structure of claim 9 wherein at least one other of said register means comprises buried register means having input terminals coupled to one or more of said output leads of said logic array means and having output terminals coupled to one or more input terminals of said logic array means, and wherein said output of said clock generating means is coupled to clock input terminals of one or more of said buried register means. 
     
     
       11. The structure of claim 10 wherein said buried register means and said output register means comprise flip flops. 
     
     
       12. The structure of claim 7 further including an end count register having an input terminal coupled to an output of said AND array and an output terminal connected to an input of said AND array. 
     
     
       13. The structure of claim 7 wherein external outputs are coupled to said state machine through respective input latches, and wherein said input latches are enabled at a rate different than the rate of said clock signal generated by said clock generating means. 
     
     
       14. A monolithic structure comprising: a state machine having one or more input terminals and a plurality of output terminals;   at least one register means having input terminals coupled to said output terminals of said state machine and having a plurality of output terminals; and   a phase-locked loop clock generating means to supply a feedback signal for comparison with a reference signal;   one of said output terminals of said register means coupled to an input of said phase-locked loop clock generating means, said register means having an associated clock input terminal coupled to an output of said phase-locked loop clock generating means.   
     
     
       15. A circuit comprising: a clock generating means having . .one or more.!. input leads and one or more output leads, at least one of said input leads being coupled for receiving an externally generated periodic reference signal, and outputting one or more clock signals on said output leads; . .and.!.   an output means having one or more input leads coupled to at least one of said output leads of said clock generating means and outputting . .a plurality of individually.!. .Iadd.one or more .Iaddend.controllable signals on one or more output leads of said output means which transition at a time referenced to transitions of said reference signal regardless of any internal propagation delays of said circuit. .;.!..Iadd., .Iaddend.   . .wherein.!. .Iadd.said clock generating means and said output means being formed on a packaged monolithic chip; and   one of said controllable signals being applied to one of said input leads of said clock generating means via a conductor external to said packaged monolithic chip so that .Iaddend.said . .plurality of individually.!. .Iadd.one or more .Iaddend.controllable signals are phase-aligned or selectively phase-shifted with said externally generated periodic reference signal.   
     
     
       16. A circuit whose output signals are made to transition at a time reference to a time of transition of an externally generated referenced signal applied to said circuit regardless of any internal propagation delays of said circuit, said circuit comprising: means for receiving an externally generated periodic reference signal and a feedback signal and for providing an output clock signal at a frequency different than said reference signal;   logic array means for receiving input signals and for performing logical functions on said input signals and for providing results of said logical functions at output terminals of said logic array means; and   one or more register means, at least one of said register means having one or more input terminals coupled to said output terminals of said logic array means and having one or more output terminals coupled to inputs of said logic array means, at least one of said register means including an output terminal for providing said feedback signal, and at least one of said register means having a clock input terminal coupled to receive said output clock signal.   
     
     
       17. The circuit of claim 16 wherein said means for receiving incorporates a phase-locked loop having a first and a second input, and having said reference signal coupled to said first input, and an output terminal of one of said register means coupled to said second input of said phase-locked loop. 
     
     
       18. The structure of claim 17 wherein said structure is a monolithic structure. 
     
     
       19. The structure of claim 18 wherein said coupling between said output terminal of one of said register means and said second input of said phase-locked loop is accomplished through a connection external to said monolithic structure. 
     
     
       20. The structure of claim 18 wherein said coupling between said output terminal of one of said register means and said second input of said phase-locked loop is accomplished through a connection internal to said monolithic structure. 
     
     
       21. The structure of claim 18 wherein said logic array means comprises: AND array means for performing functional AND operations having input leads and output leads; and   OR array means for performing functional OR operations having input leads coupled to said output leads of said AND array means and having output leads.   
     
     
       22. The structure of claim 21 wherein said AND array means is programmable. 
     
     
       23. The structure of claim 21 wherein at least one of said register means comprises output register means having input terminals coupled to said output leads of said OR array means. 
     
     
       24. The structure of claim 23 further comprising one or more buried register means having input terminals coupled to said output terminals of said logic array means and having output terminals coupled to input terminals of said logic array means, and wherein said output of said clock generating means is coupled to clock input terminals of one or more of said buried register means. 
     
     
       25. A monolithic structure comprising: a state machine having one or more input terminals and a plurality of output terminals;   at least one register means, at least one of said register means having input terminals coupled to said output terminals of said state machine and having a plurality of output terminals; and   clock generating means incorporating a phase-locked loop for generating a clock signal having a frequency different than a reference signal applied to said clock generating means, sad clock generating means having an output coupled to a clock input terminal of one or more of said register means,   one of said output terminals of said register means being coupled to an input of said clock generating means for supplying a feedback signal to be compared with said reference signal.   
     
     
       26. The structure of claim 25 wherein said reference signal is an externally generated clock signal. 
     
     
       27. The structure of claim 25 wherein said state machine comprises: AND array means for performing functional AND operations having input leads and output leads; and   OR array means for performing functional OR operations having input leads coupled to said output leads of said AND array means and having output leads.   
     
     
       28. The structure of claim 27 wherein said AND array means is programmable. 
     
     
       29. The structure of claim 27 wherein at least one of said register means comprises output register means having input terminals coupled to said output leads of said OR array means. .Iadd. 
     
     
       30.  A state machine structure comprising: a logic circuit having input leads and output leads;   at least one register means having input terminals coupled to said output leads of said logic circuit and having output terminals coupled to said input leads of said logic circuit; and   clock generating means for generating a clock signal having a frequency different than a reference signal applied to said clock generating means, said clock generating means having an output coupled to a clock input terminal of one or more of said register means;   wherein said clock generating means incorporates a phase-locked loop having first and second inputs, and having said reference signal coupled to said first input of said phase-locked loop, and an output terminal of said register means coupled to said second input of said phase-locked loop. .Iaddend..Iadd.   
     
     
       31.  A clock distribution circuit comprising: a clock receiving means having input leads and one or more output leads, at least one of said input leads being coupled for receiving an externally generated periodic reference clock signal, and outputting one or more clock signals on said output leads;   an output circuit having one or more input leads coupled to at least one of said output leads of said clock receiving means and outputting one or more signals on one or more output leads of said output circuit which transition at a time referenced to transitions of said reference signal regardless of any internal propagation delays of said clock distribution circuit,   said clock receiving means and said output circuit being formed on a packaged monolithic chip; and   one of said one or more signals being applied to one of said input leads of said clock receiving means via a conductor external to said packaged monolithic chip so that said one or more signals are phase-aligned or selectively phase-shifted with said externally generated periodic reference clock signal. .Iaddend..Iadd.   
     
     
       32.  A circuit of whose output signals are made to transition at a time referenced to a time of transition of an externally generated reference signal applied to said circuit regardless of any internal propagation delays of said circuit, said circuit comprising: means for receiving an externally generated periodic reference signal and a feedback signal and for providing an output clock signal at a frequency different than said reference signal;   a logic circuit for receiving input signals and for performing logical functions on said input signals and for providing results of said logical functions at output terminals of said logic circuit; and   one or more register means, at least one of said register means having one or more input terminals coupled to said output terminals of said logic circuit and having one or more output terminals coupled to inputs of said logic circuit, at least one of said register means including an output terminal for providing said feedback signal, and at least one of said register means having a clock input terminal coupled to receive said output clock signal. .Iaddend..Iadd.   
     
     
       33.  A clock distribution circuit comprising: means for receiving an externally generated periodic reference signal and a feedback signal on input leads and for providing an output clock signal on one or more output leads at a frequency different from said reference signal; and   an output circuit having one or more input leads coupled to at least one of said output leads of said means for receiving and outputting one or more signals on one or more output leads of said output circuit which transition at a time referenced to transitions of said reference signal regardless of any internal propagation delays of said clock distribution circuit, said means for receiving and said output circuit being formed on a packaged monolithic chip; and   one of said one or more signals being applied to one of said input leads of said means for receiving via a conductor external to said packaged monolithic chip so that said one or more signals are phase-aligned or selectively phase-shifted with said externally generated periodic reference signal. .Iaddend..Iadd.34. The circuit of claim 31 wherein said clock receiving means is a phase-locked loop. .Iaddend..Iadd.35. The circuit of claim 33 wherein said means for receiving is a phase-locked loop. .Iaddend..Iadd.36. A circuit for generating clock signals synchronized with a reference clock signal comprising:   one or more logic circuits, each having a clock input terminal and an output terminal;   a phase-locked loop having a reference input terminal, a feedback input terminal, and an output terminal;   clock input terminals of said one or more logic circuits being coupled to said output terminal of said phase-locked loop, said one or more logic circuits and said phase-locked loop being formed as an integrated circuit encapsulated in a package;   a feedback output terminal of one of said one or more logic circuits being connected to said feedback input terminal of said phase-locked loop via a conductor external to said package; and   one or more package output terminals extending from said package and connected to one or more output terminals of said one or more logic circuits, said package output terminals for providing clock signals synchronized with a reference signal connected to said reference input terminal of said phase-locked loop when said feedback output terminal is connected to said feedback input terminal of said phase-locked loop.   
     
     
        .Iaddend..Iadd.37.  The circuit of claim 36 wherein said one or more logic circuits generate signals at a frequency which is a fraction of a 
     
     
        frequency of said reference signal. .Iaddend..Iadd.38.  The circuit of claim 36 wherein said one or more logic circuits generate signals at a frequency which is a multiple of a frequency of said reference signal. .Iaddend..Iadd.39. The circuit of claim 36 wherein said one or more logic circuits generate signals at a frequency which is the same frequency as said reference signal. .Iaddend..Iadd.40. The circuit of claim 36 wherein each of said one or more logic circuits includes a storage element. .Iaddend..Iadd.41. The circuit of claim 40 wherein said storage element is a flip-flop. .Iaddend..Iadd.42. The circuit of claim 36 wherein said phase-locked loop includes a voltage controlled oscillator. .Iaddend..Iadd.43. The circuit of claim 36 wherein an output frequency of said phase-locked loop is different from a frequency of said reference 
     
     
        signal. .Iaddend..Iadd.44.  The circuit of claim 36 wherein said one or more logic circuits are clocked at an output frequency of said phase-locked loop. .Iaddend..Iadd.45. The circuit of claim 36 wherein said one or more logic circuits output a signal at an output frequency of said phase-locked loop. .Iaddend..Iadd.46. The circuit of claim 36 further comprising a means for selecting an output frequency of signals applied to said one or more package output terminals. .Iaddend..Iadd.47. A circuit for generating clock pulses comprising: a phase-locked loop having a reference signal terminal, a feedback signal terminal, and an output terminal;   a plurality of registers, each register having a clock input connected to receive a clock signal corresponding to a signal on said output terminal of said phase-locked loop, said plurality of registers having respective register output terminals, one of said register output terminals providing a feedback signal, other ones of said register output terminals providing clock pulses for external circuits;   said phase-locked loop and said plurality of registers being provided on the same monolithic circuit; and   a conductor, external to said monolithic circuit, connected between said one of said register output terminals providing said feedback signal and said feedback signal terminal of said phase-locked loop. .Iaddend..Iadd.48. The circuit of claim 47 wherein at least one of said plurality of registers generates signals at a frequency which is a fraction of a frequency of a reference signal applied to said reference signal terminal. .Iaddend..Iadd.49. The circuit of claim 47 wherein at least one of said plurality of registers generates signals at a frequency which is a multiple of a frequency of a reference signal applied to said reference signal terminal. .Iaddend..Iadd.50. The circuit of claim 47 wherein at least one of said plurality of registers generates signals at a frequency which is the same frequency as a reference signal applied to said reference signal terminal. .Iaddend..Iadd.51. The circuit of claim 47 wherein at least one of said registers is a flip-flop. .Iaddend..Iadd.52. The circuit of claim 47 wherein said phase-locked loop includes a voltage controlled oscillator. .Iaddend..Iadd.53. The circuit of claim 47 wherein an output frequency of said phase-locked loop is different from a frequency of a reference signal applied to said reference signal terminal. .Iaddend..Iadd.54. The circuit of claim 47 wherein said plurality of registers are clocked at an output frequency of said phase-locked loop. .Iaddend..Iadd.55. The circuit of claim 47 wherein said plurality of registers output signals at an output frequency of said phase-locked loop.   
     
     
        .Iaddend..Iadd.56.  The circuit of claim 47 further comprising a means for selecting an output frequency of signals applied to said one or more output terminals. .Iaddend..Iadd.57. The circuit of claim 15 wherein said clock generating means is a phase-locked loop. .Iaddend.