Solid state optically coupled electrical power switch

Abstract

Solid state optically coupled power switch with light induced or modified voltage applied or removed at one or more MOSFET gate and source electrode pairs to shift each MOSFET between its high and low impedance states and in various circuit arrays for ac or dc switching and/or cross points switching or mechanical Form C relay substitution or other purposes

What is claimed is: . .1. A solid state optically-coupled relay comprising, 
     
        to the ends of the first diode array..!.2. A solid state optically-coupled relay comprising, (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) an enhancement-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay . .switch.!. with gate, source and drain electrodes, the source and drain electrodes thereof being connected to said output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array,   (e) a depletion-mode junction FET (JFET) with source, drain and gate electrodes . .of the DMOS and.!. the gate and source electrodes of the JFET being connected to the ends of the second diode array,   the JFET providing a maximum turn-off bias to the DMOS when the JFET is at a low impedance, such low impedance condition of the JFET occurring when the second diode array is not illuminated, the JFET providing a turn on bias to the DMOS when the JFET is at a high impedance, such high impedance   
     
     
        occurring when the second diode array is illuminated. 3. . .Relay switch apparatus in accordance with either of claims 1 or 2.!. .Iadd.A solid state optically-coupled relay comprising, (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) an enhancement-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay with gate, source and drain electrodes, the source and drain electrodes thereof being connected to said output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array;   wherein said relay is .Iaddend.in directional configuration with two such output FETs connected on series opposition, the source electrodes of said two FETs being directly connected and the gate electrodes of said two FETs   
     
     
        being directly connected. 4. . .Relay switch apparatus in accordance with any of claims 1 or 2.!. .Iadd.A solid state optically-coupled relay comprising, (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) an enhancement-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay with gate, source and drain electrodes, the source and drain electrodes thereof being connected to said output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array; .Iaddend.   wherein the diode array and light emitting means are arranged in the same plane and further comprising.Iadd.:   (e) .Iaddend.. .(f).!. thin film means overlying the array and emitting   
     
     
        means and providing a refractive optical coupling path therebetween. 5. A solid state optically coupled relay comprising, (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) a depletion-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay . .switch.!. with gate, source and drain electrodes, the source and drain electrodes thereof being connected to said output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array,   (e) a depletion mode bias FET with source, drain and gate electrodes,   (e') source and drain electrodes of the bias FET being connected to the drain and gate electrode of the output FET,   (e") source and gate electrodes of the bias FET being connected to ends of   
     
     
        the diode array. .Iadd.6.  A solid state optically-coupled relay comprising, (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) an enhancement-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay with gate, source and drain electrodes, the source and drain electrodes thereof being connected to said output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array;   (e) a depletion-mode junction FET (JFET) with source, drain and gate electrodes, the gate and source electrodes of the JFET being connected to the ends of the second diode array,   wherein said relay is in directional configuration with two such output FETs connected on series opposition, the source electrodes of said two FETs being directly connected and the gate electrodes of said two FETs being directly connected. .Iaddend..Iadd.7. A solid state optically-coupled relay comprising,   (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) an enhancement-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay with gate, source and drain electrodes, the source and drain electrodes thereof being connected to said output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array;   (e) a depletion-mode junction FET (JFET) with source, drain and gate electrodes, the gate and source electrodes of the JFET being connected to the ends of the second diode array,   wherein the diode array and light emitting means are arranged in the same plane and further comprising:   (f) thin film means overlying the array and emitting means and providing a   
     
     
        refractive optical coupling path therebetween. .Iaddend..Iadd.8.  A solid state optically-coupled relay comprising, (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) an enhancement-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay with gate, source and drain electrodes, the source and drain electrodes thereof being connected to said output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array, and   (e) a bias switching device connected between the gate and source electrodes of the output FET, the gate and source electrodes having an equivalent capacitance therebetween, the bias switching device being operable in a first mode so as to provide a relatively high impedance path between the gate and source electrodes of the output FET when the light emitting means is illuminated and in a second mode so as to provide a relatively low impedance path between the gate and source electrodes of the output FET when the light emitting means is not illuminated, such that the turn-on of the output FET takes place with a time constant substantially determined by the equivalent capacitance between the gate and source electrodes of the output FET and the impedance path of the bias switching device. .Iaddend..Iadd.9. A solid state optically-coupled relay comprising,   (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) an enhancement-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay with gate, source and drain electrodes, the source and drain electrodes thereof being connected to said output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array, and   (e) a bias switching device connected across the gate and source electrodes of the output FET, the gate and source electrodes having an equivalent capacitance therebetween, the bias switching device being operable in a first mode so as to provide a relatively high impedance path between the gate and source electrodes of the output FET when the light emitting means is illuminated and in a second mode so as to provide a relatively low impedance path between the gate and source electrodes of the output FET when the light emitting means is not illuminated, such that the turn-off of the output FET takes place with a time constant substantially determined by the equivalent capacitance between the gate and source electrodes of the output FET and the impedance path of the bias switching device. .Iaddend..Iadd.10. A relay according to claim 9, wherein the bias switching device is a transistor. .Iaddend..Iadd.11. A relay according to claim 10, wherein the bias switching device is a JFET. .Iaddend..Iadd.12. A relay according to claim 10, wherein the bias switching device is a depletion-mode JFET. .Iaddend..Iadd.13. A relay according to claim 9, wherein the inherent turn-off time of the output FET, when unbaised, is a function of the time it takes to discharge the equivalent capacitance, wherein the turn-off time of the output FET in response to the change of the bias switching device from the second mode of operation to the first mode of operation is faster than the inherent turn-off time of the   
     
     
        unbiased output FET. .Iaddend..Iadd.14.  A relay according to claim 9, further including means for biasing said bias switching device. .Iaddend..Iadd.15. A relay according to claim 14, wherein said means for biasing said bias switching device includes a diode string. .Iaddend..Iadd.16. A relay according to claim 15, wherein the diode string biases the bias switching device to the second mode of operation when the light emitting means is illuminated. .Iaddend..Iadd.17. A solid state optically-coupled relay comprising, (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) an enhancement-mode vertical conduction (DMOS) MOSFET, constituting an output FET of the relay with gate, source and drain electrodes, the source and drain electrodes thereof being connected to the output terminal means and the source and gate electrodes being connected directly to the ends of the first diode array, the output FET being characterized as (i) having an equivalent capacitance between the source and gate electrodes of the output FET so that the inherent turn-on time of the out FET, when unbiased, is a function of the time it takes to charge the equivalent capacitance and (ii) being operable between an ON state wherein the signal path between the source and drain electrodes of the output FET is a relatively low impedance path and an OFF state wherein the signal path between the source and drain electrodes of the output FET is a relatively large impedance path, and   (e) a biasing switch connected between the source and gate electrodes of the output FET, the bias switch being operable in a first mode to provide a relatively low impedance path between the source and gate electrodes of the output FET when the light emitting means is not illuminated so as to maintain the output FET in an OFF state, and in a second mode to provide a relatively high impedance path between the two electrodes when the light emitting means is illuminated so as to maintain the output FET in an ON state, such that the turn-off time of the output FET in response to the change of the bias switch from the second mode of operation to the first mode of operation is faster than the inherent turn-off time of the unbiased output FET. .Iaddend..Iadd.18. A relay according to claim 17, wherein the biasing switch is a transistor. .Iaddend..Iadd.19. A relay according to claim 18, wherein said biasing switch is a JFET. .Iaddend..Iadd.20. A relay according to claim 18, wherein said biasing switch is a deletion-mode JFET. .Iaddend..Iadd.21. A relay according to claim 17, further including means for biasing said biasing switch.   
     
     
        .Iaddend..Iadd.22.  A relay according to claim 21, wherein said means for biasing includes a diode string. .Iaddend..Iadd.23. A relay according to claim 22, wherein the diode string biases the biasing switch to the second mode of operation when the light emitting means is illuminated. .Iaddend..Iadd.24. A solid state optically-coupled relay comprising, (a) solid state light emitting means,   (b) principal solid state photodetector means comprising a first diode series array optically controllable by the light emitting means,   (c) output terminal means,   (d) a first enhancement-mode vertical conduction (DMOS) MOSFET, constituting a first output FET of the relay with gate, source and drain electrodes, a second enhancement-mode vertical conduction (DMOS) MOSFET, constituting a second output FET of the relay with gate, source and drain electrodes, wherein the source electrodes of the first and second output FETs are coupled together, the drain electrodes of the first and second output FETs are respectively coupled to said output terminal means and the source and gate electrodes of the first and second output FETs are coupled to the ends of the first diode array. .Iaddend.