Dynamic video RAM incorporating single clock random port control

Abstract

An architecture for a single chip dynamic video random access memory using a single clock to operate the random port to perform refresh, memory address, and to control the internal circuitry for inputting data and addresses and for outputting data as well as modifying information in the memory circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information In the RAM and further having the write masking circuitry for modifying selected portions of the line of stored video Information between selected START and STOP bit locations within the like.

We claim: 
     
       1. An improved random port (1200) for a dynamic random access memory (1300) which stores a plurality of lines or information, said random port and said dynamic random access memory being on a single integrated circuit chip (10), said random port being connected to an address bus (100), a data bus (90) and a control but (140), said control bus delivering a read/write (R/W) signal over a single input to said integrated circuit chip, said address bus delivering the address of a line or stored information in said system, said data bus delivering source data for updating said line of stored information and the drawing rule used to update the bits in said line of stored information with said source data, said improved random port comprising: said dynamic random access memory being capable of being addressed with vector/image addresses, said control bus delivering a vector/image control signal (V/I) to identify the type of said address on said address bus, and said control bus delivering a clock signal over a single input to said integrated circuit chip,   address means 1320 connected to said address bus for receiving said vector/image address of stored information in said dynamic random access memory,   source means (1340) connected to said data bus for receiving source data and said drawing rule,   output means (1338) connected to said dynamic random access memory for delivering said stored information at said vector/image address from said memory to said data bus,   modification means (1336, 1354 and 1360) connected to said dynamic random access memory and obtaining said stored information therefrom and connected to said source means for obtaining both said source data and said drawing rule from said data bus therefrom for (a) updating said stored information with said source data and (b) for writing said modified information back into said dynamic random access memory, and   control means (1366) connected to said control bus for receiving said clock signal and said vector/image control signal from said control bus and being further connected to said address means, said source means, said output means, said modification means, and said dynamic random access memory; said control means being responsive to the receipt of said clock signal and said vector/image and read/write signals for controlling the operation of said address means, said source means, said output means, said modification means, and said dynamic random access memory.   
     
     
       2. The improved random port of claim 1 wherein said control means is a dynamic random state machine said dynamic random state machine being responsive to said vector/image and read/write signals for producing predetermined sequences of internal control pulses derived from said clock signal. 
     
     
       3. The improved random port of claim 1 wherein said source means operative with said clock signal further receives said drawing rule from said data bus, said drawing rule being the logical operation for modifying said addressed stored information and said source data being the inputted data used to perform said modification, said source means further receiving from said data bus START and STOP locations for modifying said addressed stored information, said START and STOP locations being beginning and ending bit locations in said addressed stored information between which said modification occurs, and wherein said modification means comprises: (a) means (1360) under control of said clock signal and connected to said memory for holding said stored information from said memory based upon said address in said address means,   (b) drawing rule means (1354) under control of said clock signal and connected to said holding means for obtaining said addressed stored information and connected to said data means for obtaining said drawing rule, said drawing rule means logically combining said addressed stored information with said source data according to said drawing rule logical operation to modify said addressed stored information, and   (c) write mask means (1336) under control or clock signal and connected to said source means for obtaining said START and STOP locations and connected to said memory for allowing said writing of said logical combination only between said START and STOP bit locations of said stored information.   
     
     
       4. An improved random port (1200) for a dynamic random access memory (1300) which stores a plurality of lines of information said random port and said dynamic random access memory being on a single integrated circuit chip (10), said random port being connected to an address bus (100), a data bus (90) and a control bus (140), said control bus delivering a read/write (R/W) signal over a single input to said integrated circuit chip, said address bus delivering the address of a line of stored information in said system, said data bus delivering source data for updating said line of stored information and the drawing rule used to update the bits in said line of stored information with said source data, said improved random port comprising: said dynamic random access memory being capable of storing at least one million bits and being addressed with vector/image addresses, said control bus delivering a vector/image control signal (V/I) to identify the type of said address on said address bus, and said control bus delivering a clock signal of at least one megahertz over a single input to said integrated circuit chip,   address means 1320 connected to said address bus for receiving said vector/image address of stored information in said dynamic random access memory,   source means (1340) connected to said data bus for receiving source data and said drawing rule,   source means (1338) connected to said dynamic random access memory for delivering said stored information at said vector/image address from said memory to said data bus,   modification means (1336, 1354 and 1360) connected to said dynamic random access memory and obtaining said stored information therefrom and connected to said source means for obtaining both said source data and said drawing rule from said data bus therefrom for (a) updating said stored information with said source data and (b) for writing said modified information back into said dynamic random access memory, and   a state machine (1366) connected to said control bus for receiving said clock signal and said vector/image control signal from said control bus and being further connected to said address means, said source means, said output means said modification means, and said dynamic random access memory; said state machine being responsive to the receipt of said clock signal and said vector/image and read/write signals for controlling the operation of said address means, said source means, said output means, said modification means, and said dynamic random access memory. .Iadd.   
     
     
       5.  An improved random port for a dynamic random access memory which includes a plurality of memory cells for storing information, said random port and said dynamic random access memory being on a single integrated circuit chip, said random port being connectable to an address bus, a data bus, and a control bus including an external clock signal, said improved random port comprising: address means connected to said address bus for holding a first address of information stored in said dynamic random access memory in response to a first edge of said external clock signal, and for holding a second address of said information stored in said dynamic random access memory in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge said external clock signal;   output means connected to said dynamic random access memory for delivering said stored information at said first and second addresses from said memory to said data bus; and   control means connected to said control bus for receiving said external clock signal from said control bus and being further connected to said address means, said output means and said dynamic random access memory, said control means being responsive to the receipt of said external clock signal for controlling the operation of said address means, said output means, and said dynamic random access memory. .Iaddend..Iadd.6. The improved random port of claim 5, wherein said control means is a dynamic random state machine responsive to a control input provided on said control bus for producing predetermined sequences of internal control pulses in synchronization with said external clock signal.   
     
     
        .Iaddend..Iadd. .  The improved random port of claim 5, further comprising: data input means connected to said data bus for receiving data and for holding said data in response to an edge of said external clock signal; and   writing means for writing said held data to said memory. .Iaddend..Iadd.8. A synchronous dynamic random access memory, comprising:   a memory block residing on an integrated circuit chip and including a plurality of memory cells for storing information; and   a random port residing on said integrated circuit chip and connectable to an address bus, a data bus, and a control bus including an external clock signal, said random port including: address means connected to said address bus for holding a first address of information stored in said dynamic random access memory in response to a first edge of said external clock signal and for holding a second address of said information stored in said dynamic random access memory in response to a second edge of said external clock signal, said first edge of said external clock sign b different from said second edge of said external clock signal;   output means connected to said dynamic random access memory for delivering said stored information at said first and second addresses from said memory block to said data bus; and     control means connected to said control bus for receiving said external clock signal from said control bus and being further connected to said address means, said output means and said dynamic random access memory, said control means being responsive to the receipt of said external clock signal for controlling the operation of said address means, said output means, and said memory block. .Iaddend..Iadd.9. The memory of claim 8, wherein said control means is a dynamic random state machine responsive to a control input provided on said control bus for producing predetermined sequences of internal control pulses in synchronization with said external clock signal. .Iaddend..Iadd.10. A synchronous dynamic random access memory integrated circuit comprising:   a memory block including a plurality of memory cells for storing information;   an input for receiving an external clock signal;   address input means for receiving a first address and a second address defining a location of information stored in said memory block, said address input means providing said first address as an output in response to a first edge of said external clock signal, said address input means providing said second address as an output in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock signal; and   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input   
     
     
        means. .Iaddend..Iadd.11.  The memory of claim 10, wherein said access means comprises output means for outputting information stored at said location of said memory block in response to a third edge of said external clock signal. .Iaddend..Iadd.12. The memory of claim 10, further comprising: mask information input means for receiving mask information, said mask information input means providing said mask information as an output in response to a third edge of said external clock signal, and   wherein said access means comprises: write mask means for generating a write prohibition signal for prohibiting writing information to at least one bit location in said memory block based on said mask information; and   write means for writing said information to said memory block in accordance with said write prohibition signal within a region in said memory block corresponding to said first address and said second address provided by said address input means. .Iaddend..Iadd.13. The memory of claim 12, wherein a number of bits in said mask information is less than a number of bits in said at least one bit location. .Iaddend..Iadd.14. The memory of claim 12, wherein said mask information includes information for prohibiting writing by said write means at a lower bit portion having at least one bit which is lower than a predetermined bit. .Iaddend..Iadd.15. The memory of claim 12, wherein said mask information includes information for prohibiting writing by said write means at a higher bit portion having at least one bit which is higher than a predetermined bit. .Iaddend..Iadd.16. The memory of claim 12, wherein said write means writes said information to said memory block in response to a fourth edge of said external clock signal. .Iaddend..Iadd.17. The memory of claim 11, further comprising:     control means for supplying a first enable signal and a second enable signal to said address input means in response to an external control input on an edge of said external clock signal, and for supplying an output enable signal to said output means in response to said external control input on an edge of said external clock signal, each of said first enable signal, said second enable signal and said output enable signal being synchronous with an edge of said external clock signal,   wherein said address input means provides said first address in response to said first enable signal, said address input means provides said second address in response to said second enable signal, and said output means outputs said information in response to said output enable signal. .Iaddend..Iadd.18. The memory of claim 10, wherein said access means comprising:   data input means for receiving data, said data input means providing said data as an output in response to an edge of said external clock signal; and   write means for writing said data to said memory block at a location addressed by said first address and said second address in response to an edge of said external clock signal. .Iaddend..Iadd.19. The memory of claim 18, further comprising:   control means for supplying a data enable signal to said data input means in response to an external control input on an edge of said external clock signal, and for supplying a write enable signal to said write means in response to said external control input on an edge of said external clock signal, each of said data enable signal and said write enable signal being synchronous with an edge of said external clock signal,   wherein said data input means provides said data in response to said data enable signal, and said write means writes said data in response to said write enable signal. .Iaddend..Iadd.20. The memory of claim 10, wherein said external clock signal has a frequency of about 16.7 MHz. .Iaddend..Iadd.21. The memory of claim 10, further comprising:   a serial port, including: means for receiving a serial port clock signal for controlling timing of said serial port;   serial output means; and   transfer means for transferring serial information stored in said memory block to said serial output means in response to a third edge of said external clock signal;   wherein said serial output means sequentially outputs portions of said serial information in response to respective edges of said serial port clock signal. .Iaddend..Iadd.22. The memory of claim 21, further comprising:     control means for supplying a first enable signal and a second enable signal to said address input means in response to an external control input on an edge of said external clock signal, and for supplying a transfer enable signal to said transfer means in response to said external control input on an edge of said external control input, each of said first enable signal, said second enable signal, and said transfer enable signal being synchronous with an edge of said external clock signal,   wherein said address input means provides said first address in response to said first enable signal, said address input means provides said second address in response to said second enable signal, and said transfer means transfers said serial information in response to said transfer enable signal. .Iaddend..Iadd.23. A synchronous dynamic random access memory integrated circuit comprising:   a memory block including a plurality of memory cells for storing information;   can input for receiving an external clock signal;   address input means for receiving a first address and a second address defining a location of information stored in said memory block, said address input means providing said first address as an output in response to a first enable signal, and said address input means providing said second address as an output in response to a second enable signal;   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input means;   control means for supplying said first enable signal and said second enable signal to said address input means in response to an external control input on an edge of said external clock signal, and for supplying said output enable signal to said output means in response to said external control input on an edge of said external clock signal, each of said first enable signal, said second enable signal and said output enable signal being synchronous with an edge of said external clock signal. .Iaddend..Iadd.24. The memory of claim 23, wherein said access means comprises:   data input means for receiving data, said data input means providing said data as an output in response to a data enable signal,   write means for writing said data to said memory block at a location addressed by said first address and said second address in response to a write enable signal,   wherein said control means supplies said data enable signal to said data input means in response to said external control input on an edge of said external clock signal, and supplies said write enable signal to said write means in response to said external control input on an edge of said external clock signal, each of said data enable signal and said write enable signal being synchronous with an edge of said external clock signal. .Iaddend..Iadd.25. The memory of claim 24, wherein each of said data enable signal and said write enable signal is in one of a first state   
     
     
        and a second state. .Iaddend..Iadd.26.  The memory of claim 24, wherein said control means comprises:   means for determining a next state in response to a current state and said external control input on an edge of said external clock signal; and   means for producing said first enable signal, said second enable signal, said output enable signal, said data enable signal and said write enable signal as a function of said next state. .Iaddend..Iadd.27. The memory of claim 23, wherein   said control means comprises:   means for determining a next state in response to a current state and said external control input on an edge of said external clock signal; and   means for producing said first enable signal, said second enable signal and said output enable signal as a function of said next state. .Iaddend..Iadd.28. The memory of claim 23, wherein said external clock signal has a frequency of about 16.7 MHz. .Iaddend..Iadd.29. The memory of claim 23, wherein said access means comprises output means for outputting information stored at said location of said memory block in response to an output enable signal. .Iaddend..Iadd.30. The memory of claim 29, wherein each of said first enable signal, said second enable signal and said output enable signal is in one of a first state and a second state. .Iaddend..Iadd.31. In a synchronous memory integrated circuit including a memory block having a plurality of memory cells for storing information; address input means for receiving a first address and a second address defining a location of information stored in said memory block: output means for outputting information from said memory block; and an input for receiving an external clock signal,   a method for reading information from said memory block, comprising the steps of:   a) providing said first address as an output of said address input means in response to a first edge of said external clock signal;   b) providing said second address as an output of said address input means in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock signal; and   c) outputting information stored at a location of said memory block addressed by said first address and said second address on a third edge of said external clock signal. .Iaddend..Iadd.32. The method of claim 31, further comprising the step of repeating steps of b and c. .Iaddend..Iadd.33. In a synchronous memory integrated circuit including a memory block having a plurality of memory cells for storing information; address input means for receiving a first address and a second address defining a location of information stored in said memory block; data input means for receiving data; write means for writing said data into said memory block; and an input for receiving an external clock signal,   a method for writing data into said memory block, comprising the steps of:   a) providing said first address as an output of said address input means in response to a first edge of said external clock signal;   b) providing said second address as an output of said address input means in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock signal;   c) providing said data as an output of said data input means in response to an edge of said external clock signal; and   d) writing said data into said memory block at a location addressed by said first address and said second address on an edge of said external clock   
     
     
        signal. .Iaddend..Iadd.34.  The method of claim 33, further comprising the step, of repeating steps of b and d. .Iaddend..Iadd.35. In a synchronous memory integrated circuit including a memory block having a plurality of memory cells for storing information; address input means for receiving a first address and a second address defining a location of information stored in said memory block; output means for outputting information from said memory block; data input means for receiving data: write means for writing said data into said memory block; and an input for receiving an external clock signal, a method for reading and writing information from said memory block, comprising the steps of:   a) providing said first address as an output of said address input means to response to a first edge of said external clock signal;   b) providing said second address as an output of said address input means in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock signal;   c) outputting information stored at a location of said memory block addressed by said first address and said second address on a third edge of said external clock signal;   d) providing said data as an output of said data input means in response to an edge of said external clock signal; and   e) writing said data into said memory block at said location addressed by said first address and said second address on an edge of said external   
     
     
        clock signal. .Iaddend..Iadd.36.  A synchronous dynamic random access memory integrated circuit, comprising: an input for receiving an external clock signal;   a memory block;   an address buffer in which an address from a first address and a second address bus are loaded in response to a first load enable signal and a second load enable signal, respectively, said first address and said second address representing an addressable memory location in said memory block;   means for reading information stored at said addressable memory location;   means for outputting said information read from said memory to a data bus in response to an output enable signal; and   a digital control circuit for controlling said address buffer and said means for outputting, said control circuit comprising logic clocked by said external clock signal during a read operation to generate said first and second load enable signals in response to an edge of respective clock cycles in said external clock signal, and to generate said output enable signal in response to a subsequent edge of a clock cycle in said external clock signal. .Iaddend..Iadd.37. The memory of claim 36, wherein said edges occur in consecutive clock cycles. .Iaddend..Iadd.38. The memory of claim 36, further comprising:   a data buffer in which data from a data bus is loaded in response to a data load enable signal;   means for writing said data loaded in said data buffer to said addressable memory location represented by said address loaded in said address buffer; and   wherein said control circuit logic during a write operation generates said first and second load enable signals in response to an edge of respective clock cycles in said external clock signal, and generates said data load enable signal in response to an edge of a clock cycle in said external clock signal. .Iaddend..Iadd.39. The memory of claim 38, wherein at least one of said first and second load enable signals and said data load enable signal are generated concurrently in response to the same edge.   
     
     
        .Iaddend..Iadd.40.  A synchronous dynamic random access memory integrated circuit connected to a first bus for specifying a location in said memory block and for inputting/outputting data, and a second bus for inputting an external control input defining an operation mode, comprising: a memory block including a plurality of memory cells for storing information;   an input for receiving an external clock signal;   address input means for receiving a first address and a second address through said first bus, said address input means providing said first address as an output in response to a first edge of said external clock signal, said address input means providing said second address as an output in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock signal;   access information input means for receiving access information through said first bus, said access information defining a specification of said operation mode in combination with said external control input defining said operation mode, said access information input means providing said access information as an output in response to a third edge of said external clock signal;   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input means in accordance with said operation mode and;   control means for receiving said external control input defining said operation mode through said second bus, and for controlling operations of said address input means, said access information input means and said access means in response to said external control input on an edge of said   
     
     
        external clock signal. .Iaddend..Iadd.41.  The memory of claim 40, wherein said access means comprises: write means for writing information to said memory block at a location corresponding to said first and said second address in response to a fourth edge of said external clock signal. .Iaddend..Iadd.42. The memory of claim 41,   wherein said control means supplies a first enable signal and a second enable signal to said address input means in response to an external control input on an edge of said external clock signal, supplies an access information enable signal to said access information input means in response to said external control input on an edge of said external clock signal, and supplies a write enable signal to said write means in response to said external control input on an edge of said external clock signal, each of said first enable signal, said second enable signal, said access information enable signal and said write enable signal being synchronous with an edge of said external clock signal, and   wherein said address input means provides said first address in response to said first enable signal, said address input means provides said second address in response to said second enable signal, said access information input means provides said access information in response to said access information enable signal, and said write means writes said information in   
     
     
        response to said write enable signal. .Iaddend..Iadd.43.  The memory of claim 40, further comprising: a serial port, including: means for receiving a serial port clock signal for controlling timing of said serial port;   serial output means; and   transfer means for transferring serial information stored in said memory block to said serial output means in response to a fourth edge of said external clock signal;   wherein said serial output means sequentially outputs portions of said serial information in response to respective edges of said serial port clock signal. .Iaddend..Iadd.44. The memory of claim 43,     wherein said control means supplies a first enable signal and a second enable signal to said address input means in response to an external control input on an edge of said external clock signal, and supplies a transfer enable signal to said transfer means in response to said external control input on an edge of said external clock signal, each of said first enable signal, said second enable signal and said transfer enable signal being synchronous with an edge of said external clock signal, and   wherein said address input means provides said first address in response to said first enable signal, said address input means provides said second address in response to said second enable signal, and said transfer means transfers said serial information in response to said transfer enable signal. .Iaddend..Iadd.45. A synchronous dynamic random access memory integrated circuit which operates by use of edges of an external clock signal, said memory comprising:   a memory block including a plurality of memory cells for storing information;   an input for receiving said external clock signal;   address input means for receiving a first address and a second address, said address input means providing said first address as an output in response to a first edge of said external clock signal, said address input means providing said second address as an output in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock signal;   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input means; and   control means for receiving an external control input indicating a read/write mode defining one of a read mode and a write mode, and for changing said read/write mode based on a difference of level of said external control input at two successive edges of said edges of said   
     
     
        external clock signal. .Iaddend..Iadd.46.  The memory of claim 45, wherein: said first address provided by said address input means is maintained before and after a level change of said external control input resulting in the difference of level. .Iaddend..Iadd.47. The memory of claim 45, wherein said access means comprises:   output means for outputting information stored at said location of said memory block in response to a third edge of said external clock signal. .Iaddend..Iadd.48. The memory of claim 47,   wherein said control means supplies a first enable signal and a second enable signal to said address input means in response to said external control input on an edge of said external clock signal, and supplies an output enable signal to said output means in response to said external control input on an edge of said external clock signal, each of said first enable signal, said second enable signal and said output enable signal being synchronous with an edge of said external clock signal, and   wherein said address input means provides said first address in response to said first enable signal, said address input means provides said second address in response to said second enable signal, and said output means outputs said information in response to said output enable signal. .Iaddend..Iadd.49. The memory of claim 45, wherein said access means comprises:   data input means for receiving data, said data input means providing said data as an output in response to a third edge of said external clock signal; and   write means for writing said data to said memory block at a location corresponding to said first and said second address in response to a fourth edge of said external clock signal. .Iaddend..Iadd.50. The memory of claim 49,   wherein said control means supplies a data enable signal to said data input means in response to said external control input on an edge of said external clock signal, and supplies a write enable signal to said write means in response to said external control input on an edge of said external clock signal, each of said data enable signal and said write enable signal being synchronous with an edge of said external clock signal,   wherein said data input means provides said data in response to said data enable signal, and said write means writes said data in response to said write enable signal. .Iaddend..Iadd.51. The memory of claim 45, further comprising:   a serial port, including: means for receiving a serial port clock signal for controlling timing of said serial port;   serial output means; and   transfer means for transferring serial information stored in said memory block to said serial output means in response to a third edge of said external clock signal;   wherein said serial output means sequentially outputs portions of said serial information in response to respective edges of said serial port     
     
     
        clock signal. .Iaddend..Iadd.52.  The memory of claim 51, wherein said control means supplies a first enable signal and a second enable signal to said address input means in response to said external control input on an edge of said external clock signal, and supplies a transfer enable signal to said transfer means in response to said external control input on an edge of said external clock signal, each of said first enable signal, said second enable signal and said transfer enable signal being synchronous with an edge of said external clock signal, and   wherein said address input means provides said first address in response to said first enable signal, said address input means provides said second address in response to said second enable signal, and said transfer means transfers said serial information in response to said transfer enable signal. .Iaddend..Iadd.53. A synchronous semiconductor memory integrated circuit comprising:   a memory block including a plurality of memory cells for storing information;   an input for receiving an external clock signal;   address input means for receiving a first address and a second address, said address input means providing said first address as an output in response to an edge of said external clock signal, said address input means providing said second address as an output in response to an edge of said external clock signal;   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input means and;   control means for outputting an internal control signal defining a timing of an internal operation of said synchronous semiconductor memory in response to an external control input on an edge of said external clock signal;   wherein said control means generates new state information in accordance with an external control input and state information output in response to a first edge of said external clock signal, and outputs a new internal control signal based on said new state information in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock   
     
     
        signal. .Iaddend..Iadd.54.  The memory of claim 53, wherein said external control input is on said second edge of said external clock signal. .Iaddend..Iadd.55. The memory of claim 54, wherein said control means generates further new state information in accordance with an external control input on a third edge of said external clock signal and said new state information, and outputs a further new internal control signal based on said further new state information in response to said third edge of said external, clock signal, said second edge of said external clock signal being different from said third edge of said external clock signal. .Iaddend..Iadd.56. The memory of claim 53, wherein said second edge of said external clock signal is the next edge to said first edge of said external clock signal. .Iaddend..Iadd.57. The memory of claim 53, wherein a first enable signal and a second enable signal are included in different internal control signals, said address input means provides said first address in response to said first enable signal, and said address input means provides said second address in response to said second enable signal. .Iaddend..Iadd.58. The memory of claim 53, wherein: said internal control signal is a precharge control signal provided to said   
     
     
        memory block. .Iaddend..Iadd.59.  The memory of claim 53, wherein said access means comprises: output means for outputting information stored at said location of said memory block in response to a third edge of said external clock signal. .Iaddend..Iadd.60. The memory of claim 59, wherein a first enable signal, a second enable signal and an output enable signal are included in different internal control signals, said address input means provides said first address in response to said first enable signal, said address input means provides said second address in response to said second enable signal, and said output means outputs said information in response to said output enable signal. .Iaddend..Iadd.61. The memory of claim 53, wherein said access means comprises:   data input means for receiving data, said data input means providing said data as an output in response to a third edge of said external clock signal; and   write means for writing said data to said memory block at a location corresponding to said first and said second address in response to a fourth edge of said external clock signal. .Iaddend..Iadd.62. The memory of claim 61, wherein a data enable signal and a write enable signal are included in different internal control signals, said data input means provides said data in response to said data enable signal, and said write means writes said data in response to said write enable signal. .Iaddend..Iadd.63. The memory of claim 53, further comprising:   a serial port, including: means for receiving a serial port clock signal for controlling timing of said serial port;   serial output means; and   transfer means for transferring serial information stored in said memory block to said serial output means in response to a third edge of said external clock signal;   wherein said serial output means sequentially outputs portions of said serial information in response to respective edges of said serial port     
     
     
        clock signal. .Iaddend..Iadd.64.  The memory of claim 63, wherein a first enable signal, a second enable signal and a transfer enable signal are included in different internal control signals, said address input means provides said first address in response to said first enable signal, said address input means provides said second address in response to said second enable signal, and said transfer means transfers said serial information in response to said transfer enable signal. .Iaddend..Iadd.65. The memory of claim 53, wherein said state information may be any one of a first state information indicating an initial state and a plurality of second state information indicating respective states other than said initial state, and with respect to at least one of the plurality of second state information when said state information output in response to said first edge of said external clock signal is said at least one second state information, said new state information may be any one of a predefined plurality of second state information from among said plurality of second state information, each of said predefined plurality of second state information indicating respective states other than said initial state. .Iaddend..Iadd.66. A synchronous dynamic random access memory integrated circuit a plurality of memory blocks including a plurality of memory cells for storing information;   an input for receiving an external clock input;   address input means for receiving a first address and a second address, said address input means providing said first address as an output in response to a first edge of said external clock input, said address input means providing said second address as an output in response to a second edge of said external clock input, said first edge of said external clock input being different from said second edge of said external clock input; and   output means for sequentially outputting a plurality of data which belong to separately addressable locations in said memory blocks at substantially a same interval, said plurality of data including data stored at a location in said memory blocks corresponding to said first address and said second address provided by said address input means. .Iaddend..Iadd.67. The memory of claim 66, wherein:   prior to completing outputs of a plurality of data which belong to a first separately addressable location, a plurality of data which belong to a second separately addressable location and which are stored in said memory cells of said memory blocks are accessed, said first separately addressable location being different from said second separately addressable location. .Iaddend..Iadd.68. A synchronous dynamic random access memory integrated circuit comprising:   a memory block including a plurality of memory cells for storing information;   an input for receiving an external clock signal;   address input means for receiving a first address and a second address, said address input means providing said first address as an output in response to a first enable signal, said address input means providing said second address as an output in response to a second enable signal;   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input means in response to a third enable signal; and   control means for receiving a first external control input indicating one of a read mode and a write mode and a second external control input which is different from said first external control input, for generating said third enable signal based on said first external control input and generating at least one of said first enable signal and said second enable signal based on said second external control input, and for supplying said third enable signal to said access means in response to an edge of said external clock signal and supplying at least one of said first enable signal and said second enable signal to said address input means in response to an edge of said external clock signal. .Iaddend..Iadd.69. A synchronous dynamic random access memory integrated circuit which operates by use of edges of an external clock signal, said memory comprising:   a memory block including a plurality of memory cells for storing information;   an input for receiving an external clock signal;   address input means for receiving a first address and a second address, said address input means providing said first address as an output in response to a first edge of said external clock signal, said address input means providing said second address as an output in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock signal;   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input means;   control means for receiving an external control input indicating whether or not a precharge operation is performed, and for changing whether said precharge operation is performed based on a difference of level of said external control input at two successive edges of said edges of said   
     
     
        external clock signal. .Iaddend..Iadd.70.  The memory of claim 69, wherein said external control input serves as a signal indicating whether or not an access to said memory block is performed. .Iaddend..Iadd.71. A synchronous semiconductor memory integrated circuit comprising: a memory block including a plurality of memory cells for storing information;   an input for receiving an external clock signal;   address input means for receiving a first address and a second address, said address input means providing said first address as an output in response to an edge of said external clock signal, said address input means providing said second address as an output in response to an edge of said external clock signal;   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input means; and   control means for outputting an internal control signal defining a timing of an internal operation of said synchronous semiconductor memory in response to an external control input on an edge of said external clock signal;   wherein said control means comprises a random state machine.   
     
     
        .Iaddend..Iadd.2.  The memory of claim 71, wherein said random state machine determines a new state based on said external control input and a current state, and outputs said internal control signal based on said new state in response to an edge of said external clock signal. .Iaddend..Iadd.73. The memory of claim 72, wherein said random state machine comprises: decoding means for decoding said new state so as to output said internal control signal. .Iaddend..Iadd.74. The memory of claim 72, wherein said current state and said new state may be any one of a first state indicating an initial state and a plurality of second states each indicating a state other than said initial state, and with respect to at least one of the plurality of second states when said current state is said at least one second state, said new state may be any one of a predefined plurality of second states from among said plurality of second states, each of said predefined plurality of second states indicating states other than said initial state. .Iaddend..Iadd.75. A synchronous dynamic random access memory integrated circuit comprising:   a memory block including a plurality of memory cells for storing information;   an input for receiving an external clock signal;   an address input means for receiving a first address and a second address, said address input means providing said first address as an output in response to a first edge of said external clock signal, said address input means providing said second address as an output in response to a second edge of said external clock signal, said first edge of said external clock signal being different from said second edge of said external clock signal;   access means for accessing a location in said memory block corresponding to said first address and said second address provided by said address input means; and   control means for receiving a predetermined set of control signals provided from outside of said synchronous dynamic random access memory, for making a transition from a state to a next state in accordance with said predetermined set of control signals on respective edges of said external clock signal, and for outputting an internal control signal defining a timing of an internal operation of said synchronous dynamic random access memory based on the said next state;   wherein said predetermined set of control signals include a first control signal and a second control signal, said internal operation represents a write operation when said first control signal is in a first logic level and said second control signal is in a second logic level, and said internal operation represents a read operation when said first control signal is in a third logic level which is different from the first logic level and said second control signal in said second logic level. .Iaddend..Iadd.76. The memory of claim 75, wherein a logic level of said first control signal is changed during a period when said second control signal is in said second logic level, and said operation of said synchronous dynamic random access memory is changed between said read operation and said write operation in accordance with said logic level change of said first control signal without reverting back to a state prior to starting either said read operation or said write operation. .Iaddend.