Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines

Abstract

A synchronous dynamic random access memory device allows an external device to sequentially access read-out data bits in synchronous with a system clock signal, and a column addressing system incorporated in the synchronous dynamic random access memory device forms a plurlaity of pipeline stages together with an input/output unit for sequentially supplying data bits to a data port in response to a column address internally incremented in synchronism with the system clock signal, thereby propagating the data bits through a single data bus.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a) a memory cell array having plurality of addressable memory cells for storing a plurality of data bits selectively assigned with row addresses and column addresses;   b) a row addressing system responsive to an external row address signal indicative of one of said row addresses for selecting a row of memory cells from said plurality of addressable memory cells;   c) a timing controller for producing a plurality of internal control signals for sequentially supplying data bits selected from said plurality of data bits to outside of said semiconductor memory device;   d) an interface unit coupled with a data port for transferring said data bits to the outside of said semiconductor memory device;   e) a single shared data bus coupled with said interface unit for sequentially propagating said data bits to said interface unit; and   f) a column addressing system coupled with said single shared data bus, and having f-1) a column address buffer sub-system operative to store one of said column addresses represented by an external column address signal, and responsive to first internal control signals of said plurality of internal control signals for changing said one of said column addresses a predetermined number of times, and   f-2) a column address decoder/selector sub-system forming a plurality of pipeline stages together with said interface unit, said plurality of pipeline stages being responsive to second internal control signals of said plurality of internal control signals so as to successively transfer said data bits, identified by said one of said column addresses and said column addresses changed by said column address buffer sub-system through said single shared data bus to said data port,     said column address decoder/selector subsystem comprising a plurality of column address decoder/selector units coupled through said single shared data bus with said interface unit, each of said plurality of column address decoder/selector units having a first column address decoder responsive to lower column address bits for producing a first column address decoded signal,   a second column address decoder responsive to higher column address bits for producing a second column address decoded signal, said lower and higher column address bits being indicative of said one of said column addresses and said column addresses changed said predetermined number of times,   a latch circuit responsive to one of said second internal control signals for storing said first column address decoded signal,   a read amplifier for amplifying one of said data bits,   a read-out circuit responsive to said first column address decoded signal stored in said latch circuit for transferring said one of said data bits to said read amplifier, and   a switching unit enabled with said one of said second internal control signals and responsive to said second column address decoded signal for transferring said one of said data bits to said single shared data bus, said switching unit and said read-out circuit controlled by said latch circuit forming parts of said plurality of pipeline stages.   
     
     
       2. The semiconductor memory device as set forth in claim 1, in which said column address buffer sub-system sequentially changes said one of said column addresses said predetermined number of times. 
     
     
       3. The semiconductor memory device as set forth in claim 1, in which said interface unit has a pair of flip-flop circuits responsive to another of said second internal control signals for sequentially storing said data bits, said pair of flip-flop circuits forming a part of said plurality of pipeline stages. .Iadd. 
     
     
       4.  A semiconductor memory device, comprising: a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with addresses;   a selection circuit coupled to said memory cells for accessing said memory cells;   a buffer circuit supplied with address bits in synchronization with a clock signal;   an internal buffer receiving a predetermined number of said address bits;   a logic circuit, responsive to said predetermined number of address bits representing a value, for generating an internal set of address bits representing another value in synchronization with said clock signal;   an internal output buffer selectively coupled to receive one of: said predetermined number of address bits and said internal set of address bits, via a first switch, said internal output buffer being coupled to said selection circuit, said selection circuit having a first access to said memory cells corresponding to a value of said predetermined number of address bits and second access to said memory cells corresponding to a value of said internal set of address bits; and   a control circuit generating control information which is supplied to said first switch to first select said internal buffer supplying said predetermined number of address bits and subsequently to select said logic circuit generating said internal set of address bits, thereby accelerating said first and second accesses to said memory cells..Iaddend..Iadd.5. The semiconductor memory device as claimed in claim 4, further comprising:   a register receiving external information indicating a row of said memory cells, said selection circuit having said first access to one of said memory cells corresponding to said external information and to said address bits from said internal buffer and subsequently said second access to another memory cell corresponding to said external information and to said address bits from said logic circuit..Iaddend..Iadd.6. The semiconductor memory device as claimed in claim 5, wherein said first access is responsive to said address bits supplied from said internal buffer without passing through said logic circuit..Iaddend..Iadd.7. The semiconductor memory device as claimed in claim 5, wherein said logic circuit includes an adder to increment said value of said predetermined number of address bits..Iaddend..Iadd.8. The semiconductor memory device as claimed in claim 7, further comprising a latch circuit associated with said logic circuit and a second switch, said second switch selectively coupling said logic circuit to said internal buffer, an output of said latch circuit further incrementing said predetermined number of address bits and providing corresponding further accesses to said memory cells in sequence..Iaddend..Iadd.9. The semiconductor memory device as claimed in claim 5, wherein said logic circuit includes an inverter for inverting one bit of said predetermined number of address bits and a logic gate for selectively inverting another bit of said predetermined number of address bits according to a value of said one bit of said predetermined number of address bits..Iaddend..Iadd.10. The semiconductor memory device as claimed in claim 4, wherein said first switch comprises a parallel combination of n-channel type and p-channel type field effect transistors..Iaddend..Iadd.11. A semiconductor memory device, comprising:   a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with addresses;   a selection circuit coupled to said memory cells for accessing said memory cells;   an input buffer receiving address bits;   a first address signal path between said input buffer and said selection circuit for providing a first number of said address bits to said selection circuit;   a second address signal path between said input buffer and said selection circuit, including a first internal buffer and a second internal buffer, for providing a second number of said address bits to said selection circuit; and   a third address signal path between said first internal buffer and said second internal buffer including a first logic gate and a latch for providing said second number of address bits representing address information generated by said first logic gate and different from address information provided on said second address signal path, wherein said selection circuit is responsive to address information from said first address signal path and address information from one of said second and third address signal paths selected in sequence to provide a burst access to said memory cells..Iaddend..Iadd.12. The semiconductor memory device as claimed in claim 11, wherein address bits in said first internal buffer are directly supplied to said second internal buffer to accelerate said burst access..Iaddend..Iadd.13. The semiconductor memory device as claimed in claim 11, further comprising a second logic gate for detecting a match between outputs from said first internal buffer and said first logic gate to indicate the end of said burst access..Iaddend..Iadd.14. The semiconductor memory device as claimed in claim 13, wherein said second logic gate is of exclusive-OR type..Iaddend..Iadd.15. The semiconductor memory device as claimed in claim 11, wherein said logic gate includes an adder to increment said second number of said address bits and supplies said incremented bits to said latch during a first operational period of the device, said second number of address bits being transferred to said second internal buffer without passing though said adder during said first operational period of the device..Iaddend..Iadd.16. A semiconductor memory device, comprising:   a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with addresses;   a selection circuit coupled to said memory cells for accessing said memory cells;   a buffer receiving address bits in synchronization with a clock signal;   a signal path, coupled between said buffer and said selection circuit, for selectively transferring said address bits to said selection circuit;   a logic circuit, coupled between said buffer and said selection circuit, for incrementing said address bits and selectively transferring the incremented address bits to said selection circuit; and   a timing control circuit sequentially selecting, in synchronization with said clock signal, said signal path and said logic circuit to be coupled to said selection circuit for respectively performing a first and a subsequent part of a burst access of said memory cells..Iaddend..Iadd.17. A semiconductor memory device, comprising:   a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with row addresses and column addresses;   a selection circuit providing burst access to said memory cells and being responsive to a plurality of sets of address bits from an internal address path to select columns of memory cells;   a buffer receiving one of said sets of address bits; and   an address generating circuit,   said buffer supplying said one of said sets of address bits to said internal address path and to said address generating circuit in common during a first operation cycle of said burst access, said selection circuit being responsive to said one of said sets of address bits appearing on said internal address path during said first operation cycle and thereby selecting a corresponding one of said columns, said address generating circuit incrementing said one of said sets of address bits received during said first operation cycle and thereby supplying incremented address bits to said internal address path during a second operation cycle of said burst access, said selection circuit being further responsive to said incremented address bits appearing on said internal address path during said second operation cycle and thereby selecting another of said columns..Iaddend..Iadd.18. The semiconductor memory device as claimed in claim 17, wherein said address generating circuit includes a first circuit portion for inverting a low bit of address bits supplied thereto and a second circuit portion for selectively inverting a high bit of address bits supplied thereto according to a value of said low bit, said first and second circuit portions being selectively enabled during said burst access according to internal control information indicating a burst length..Iaddend..Iadd.19. The semiconductor memory device as claimed in claim 18, further comprising a logic gate comparing an output from said buffer and an output from said address generating circuit to indicate an end of said burst access..Iaddend..Iadd.20. The semiconductor memory device as claimed in claim 19, further comprising a transfer gate disposed between said buffer and said address path for directly providing said one of sets of address bits during said first operation cycle..Iaddend..Iadd.21. A semiconductor memory device, comprising:   a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with addresses;   a selection circuit coupled to said memory cells for accessing said memory cells;   an input port supplied with address bits;   a first address path coupled between said input port and said selection circuit;   a second address path coupled between said input port and said selection circuit, said second address path including a logic circuit to logically change at least one of said address bits; and   a switch selectively coupling said first address path and said second address path to said selection circuit in sequence, thereby causing said selection circuit to access said memory cells in sequence..Iaddend..Iadd.22. The semiconductor memory device as claimed in claim 21, wherein said second address path further includes a latch and said logic circuit includes an adder, an input of said latch being coupled to an output of said adder, and an output of said latch being coupled to an input of said adder, said adder and said latch causing said address bits to be repeatedly incremented..Iaddend..Iadd.23. The semiconductor memory device as claimed in claim 21, further comprising a detector responsive to address bits in said first address path and address bits in said second address path to indicate an end of a sequence of accesses..Iaddend..Iadd.24. A semiconductor memory device, comprising:   a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with addresses;   a selection circuit coupled to said memory cells for accessing said memory cells;   an input latch receiving an initial set of address bits in response to an external command;   an internal latch receiving an incremented set of address bits generated from said initial set of address bits at a first clock cycle of the device;   an adder responsive to said internal latch and providing a further incremented set of address bits to said internal latch at each of subsequent cycles prior to another external command being applied to said device, said selection circuit accessing said memory cells according to said initial, incremented and further incremented sets of address bits in sequence; and   an address signal path in parallel with said internal latch and said adder for transferring said initial set of address bits to said selection circuit during said first clock cycle..Iaddend..Iadd.25. A semiconductor memory device, comprising:   a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with addresses;   an incrementer for generating internal address bits in sequence;   a selection circuit coupled to said memory cells for providing burst access to said memory cells in response to said internal address bits in sequence;   a burst end detector coupled to said incrementer and responsive to reference bits, said incrementer performing in common generation of said internal address bits and detection of an end of said burst access..Iaddend..Iadd.26. The semiconductor memory device as claimed in claim 25, wherein said incrementer is synchronized with a system clock..Iaddend..Iadd.27. A semiconductor memory device, comprising:   a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with row addresses and column addresses;   a control circuit indicating one of a first burst access and a second burst access of said memory cells;   a selection circuit responsive to a plurality of sets of address bits from an internal address path to select columns of memory cells;   a buffer receiving one of said sets of address bits;   an address generating circuit including an incrementer, said buffer supplying said one of said sets of address bits to said internal address path and to said address generating circuit in common during a first operation cycle of each of said first and second burst accesses, said selection circuit being responsive to said one of said sets of address bits appearing on said internal address path during said first operation cycle and thereby selecting a corresponding one of said columns, said address generating circuit incrementing, during said first burst access, said one of said sets of address bits received during said first operation cycle and thereby supplying incremented bits to said internal address path during a second operation cycle of said first burst access, said selection circuit being further responsive to said incremented bits appearing on said internal address path during said second operation cycle and thereby selecting another of said columns;   a first gate circuit enabled during said second burst access for supplying predetermined bits to said address generating circuit, said address generating circuit incrementing said predetermined bits; and   a second gate circuit enabled during said second burst access responsive to an output from said buffer and an output from said address generating circuit for providing output bits to said internal address path during a second operation cycle of said second burst access, said selection circuit being further responsive to said output bits and thereby selecting a column other than said one of said columns..Iaddend..Iadd.28. A semiconductor memory device, comprising:   a memory cell array having a plurality of addressable memory cells for storing a plurality of data bits selectively assigned with addresses, wherein said memory cells are accessed during a sequential burst wherein internal address bits are sequentially incremented beginning with initial address bits provided externally and during an interleave burst wherein internal address bits are generated in a logic circuit responsive to said initial address bits and a sequence of incremented bits beginning with predetermined bits;   an incrementer associated with an input gate for setting an initial value of said incrementer according to said initial address bits during said sequential burst and according to said predetermined bits during said interleave burst, said incrementer being further associated with an output gate selectively supplying output bits from said incrementer to said logic circuit during said interleave burst, said logic circuit being responsive to said initial address bits, said incrementer thereby providing internal address bits of the device in common in said sequential burst and said interleave burst..Iaddend..Iadd.29. A method for accessing a semiconductor memory device, comprising steps of:   a) applying a command to said memory device to incorporate a set of address bits;   b) applying said set of address bits to a logic circuit;   c) changing said set of address bits to generate another set of address bits in said logic circuit;   d) applying said set of address bits to a selector without passing through said logic circuit;   e) selecting one of an array of memory cells according to said set of address bits in step d);   f) applying said another set of address bits to said selector; and   g) selecting another of said memory cells according to said another set of address bits in step f)..Iaddend..Iadd.30. The method as claimed in claim 29, further comprising steps of:   h) incrementing in said logic circuit an applied set of address bits to generate an output set of incremented address bits;   i) applying said output set to said logic circuit;   j) selecting another one of said memory cells according to said output set in step h)   k) repeating steps h), i) and j);   l) comparing said address bits in step a) with said incremented address bits in step h); and   m) indicating in response to step l) an end of a burst access..Iaddend.