Control circuit of dynamic random access memory

Abstract

A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.

What is claimed is: 
     
       1. A control circuit of a memory system including a dynamic random access memory, said control circuit comprising: a first integrated circuit formed on a common substrate and including: a control signal generator responsive to an external memory access request signal and generating a control signal for controlling an operation timing of the dynamic random access memory; and   an address signal generator generating an address signal specifying an address of the dynamic random access memory to be accessed and supplying the address signal to the dynamic random access memory; and     a second integrated circuit including a data read/write device reading data from the dynamic random access memory and writing data in the dynamic random access memory.   
     
     
       2. A control circuit according to claim 1, said first integrated circuit further comprising: a first output circuit supplying the control signal generated by said control signal generator to the dynamic random access memory; and   a second output circuit supplying the address signal generated by the address signal generator to the dynamic random access memory;   wherein the first output circuit and the second output circuit are each formed of a common type gate circuit and are disposed on the common substrate of the first integrated circuit.   
     
     
       3. A control circuit according to claim 1, wherein the dynamic random access memory comprises a plurality of memory banks and said first integrated circuit supplies the control signal generated by said control signal generator to each of said plurality of memory banks. 
     
     
       4. A control circuit according to claim 3, wherein said second integrated circuit is provided for each of said memory banks. 
     
     
       5. A control circuit of a memory system including a dynamic random memory, said control circuit comprising: a first integrated circuit formed on a common substrate and including: a control signal generator responsive to an external memory access request signal and generating a control signal for controlling an operation timing of the dynamic random access memory; and   an address signal generator generating an address signal specifying an address of the dynamic random access memory to be accessed and supplying the address signal to the dynamic random access memory; and     a second integrated circuit including: a data read/write device reading data from the dynamic random access memory and writing data in the dynamic random access memory: and   an adder adding an error check code to data to be written in the dynamic random access memory to detect and correct errors on the basis of the error check code in data read from the dynamic random access memory.     
     
     
       6. A control circuit according to claim 5, wherein the address signal generated by the address signal generator includes a row address signal and a column address signals and wherein the control signal generated by the control signal generator includes a row address strobe signal indicating a reading timing of the row address signal, a column address strobe signal indicating a reading timing of the column address signal, and a write enable signal indicating whether the memory access request signal is a writing request or a reading request. 
     
     
       7. A control circuit according to claim 6, said first integrated circuit further comprising: a first output circuit supplying the control signal generated by said control signal generator to the dynamic random access memory; and   a second output circuit supplying the address signal generated by the address signal generator to the dynamic random access memory;   wherein the first output circuit and the second output circuit are each formed of a common type gate circuit and are disposed on the common substrate of the first integrated circuit.   
     
     
       8. A control circuit according to claim 7, wherein the dynamic random access memory comprises a plurality of memory banks and said first integrated circuit supplies the control signal generated by said control signal generator to each of said plurality of memory banks. 
     
     
       9. A control circuit according to claim 8, wherein said second integrated circuit is provided for each of said memory banks. 
     
     
       10. A control circuit according to claim 5, said first integrated circuit further comprising: a first output circuit supplying the control signal generated by said control signal generator to the dynamic random access memory; and   a second output circuit supplying the address signal generated by the address signal generator to the dynamic random access memory;   wherein the first output circuit and the second output circuit are each formed of a common type gate circuit and are disposed on the common substrate of the first integrated circuit.   
     
     
       11. A control circuit according to claim 5, wherein the dynamic random access memory comprises a plurality of memory banks and said first integrated circuit supplies the control signal generated by said control signal generator to each of said plurality of memory banks. 
     
     
       12. A control circuit according to claim 11, wherein said second integrated circuit is provided for each of said memory banks. 
     
     
       13. A control circuit of a memory system including a dynamic random access memory, said control circuit comprising: a first integrated circuit formed on a common substrate and including: a control signal generator responsive to an external memory access request signal and generating a control signal for controlling an operation timing of the dynamic random access memory; and   an address signal generator generating an address signal specifying an address of the dynamic random access memory to be accessed and supplying the address signal to the dynamic random access memory: and     a second integrated circuit including a data read/write device reading data from the dynamic random access memory and writing data in the dynamic random access memory;   wherein the address signal generated by the address signal generator includes a row address signal and a column address signal, and wherein the control signal generated by the control signal generator includes a row address strobe signal indicating a reading timing of the row address signal, a column address strobe signal indicating a reading timing of the column address signal, and a write enable signal indicating whether the memory access request signal is a writing request or a reading request.   
     
     
       14. A control circuit according to claim 13, said first integrated circuit further comprising: a first output circuit supplying the control signal generated by said control signal generator to the dynamic random access memory; and   a second output circuit supplying the address signal generated by the address signal generator to the dynamic random access memory;   wherein the first output circuit and the second output circuit are each formed of a common type gate circuit and are disposed on the common substrate of the first integrated circuit.   
     
     
       15. A control circuit according to claim 13, wherein the dynamic random access memory comprises a plurality of memory banks and said first integrated circuit supplies the control signal generated by said control signal generator to each of said plurality of memory banks. 
     
     
       16. A control circuit according to claim 15, wherein said second integrated circuit is provided for each of said memory banks. 
     
     
       17. A control circuit of a memory system including a dynamic random access memory, comprising: a first integrated circuit responsive to an external memory access request signal and performing control of an operation timing and designation of an address of the dynamic random access memory; and   a second integrated circuit independent of said first integrated circuit and including a read/write circuit reading data from the dynamic random access memory and writing data in the dynamic random access memory;   said second integrated circuit further comprising an adder adding an error check code to data to be written in the dynamic random access memory to detect and correct errors on the basis of the error check code in data read from the dynamic random access memory.   
     
     
       18. A control circuit according to claim 17, said first integrated circuit formed on a common substrate and including: a control signal generator responsive to the external memory access request signal and generating a control signal for controlling an operation timing of the dynamic random access memory; and   an address signal generator responsive to an address signal specifying an address of the dynamic random access memory to be accessed and supplying the address signal to the dynamic random access memory.   
     
     
       19. A control circuit according to claim 18, wherein the address signal generated by the address signal generator includes a row address signal and a column address signal, and wherein the control signal generated by the control signal generator includes a row address strobe signal indicating a reading timing of the row address signal, a column address strobe signal indicating a reading timing of the column address signal, and a write enable signal indicating whether the memory access request signal is a writing request or a reading request. 
     
     
       20. A control circuit according to claim 18, said first integrated circuit further comprising: a first output circuit supplying the control signal generated by said control signal generator to the dynamic random access memory; and   a second output circuit supplying the address signal generated by the address signal generator to the dynamic random access memory;   wherein the first output circuit and the second output circuit are each formed of a common type gate circuit and are disposed on the common substrate of the first integrated circuit.   
     
     
       21. A control circuit according to claim 18, wherein the dynamic random access memory comprises a plurality of memory banks and said first integrated circuit supplies the control signal generated by said control signal generator to each of said plurality of memory banks. 
     
     
       22. A control circuit according to claim 21, wherein said second integrated circuit is provided for each of said memory banks. .Iadd. 
     
     
       23.  A control circuit for accessing a memory system including a dynamic random access memory, said control circuit comprising: a first integrated circuit including: a control signal generator generating a control signal for controlling an operation timing of the memory system; and   an address signal generator generating an address signal specifying an address of the memory system to be accessed and supplying the address signal to the memory system; and     a second integrated circuit including a data read/write device reading data from the memory system and writing data in the memory system..Iaddend..Iadd.24. A control circuit according to claim 23, wherein said control signal generator generating the control signal is responsive to an external memory access request signal..Iaddend..Iadd.25. A control circuit according to claim 23, wherein said control signal generator and said address signal generator are formed in a single LSI circuit..Iaddend..Iadd.26. A control circuit according to claim 23, wherein the memory system comprises a plurality of memory banks and said first integrated circuit supplies the control signal generated by said control signal generator to at least one of said plurality of memory banks..Iaddend..Iadd.27. A control circuit according to claim 26, further comprising a plurality of second integrated circuits wherein one of said second integrated circuit is provided for each of said memory banks..Iaddend..Iadd.28. A control circuit according to claim 26, wherein the address signal generated by the address signal generator includes a row address signal and a column address signal, and wherein the control signal generated by the control signal generator includes a row address strobe signal indicating a reading timing of the row address signal, a column address strobe signal indicating a reading timing of the column address signal, and a write enable signal indicating whether the memory access request signal is a writing request or a reading request..Iaddend..Iadd.29. A control circuit according to claim 23, said second integrated circuit further comprising:   an adder adding an error check code to data to be written in the memory system to detect and correct errors on the basis of the error check code   
     
     
        in data read from the memory system..Iaddend..Iadd.30.  A control circuit according to claim 23, wherein said address signal generator includes a register..Iaddend..Iadd.31. A control circuit according to claim 23, wherein said data read/write device includes a register..Iaddend..Iadd.32. A control circuit for accessing a memory system including a dynamic random access memory, said control circuit comprising: a first LSI circuit including: a control circuit that provides a control signal that controls an operation timing of the memory system; and   an address register that supplies a memory address signal, that specifies an address of the memory system to be accessed, to the memory system; and   a second LSI circuit including a data read/write register for reading data from the memory system and writing data in the memory system..Iaddend..Iadd.33. A control circuit of a memory system including a dynamic random access memory, comprising:     a first integrated circuit performing control of an operation timing and designation of an address of the dynamic random access memory; and   a second integrated circuit independent of said first integrated circuit and including a read/write circuit reading data from the dynamic random access memory and writing data in the dynamic random access memory;   said second integrated circuit further comprising an adder adding an error check code to data to be written in the dynamic random access memory to detect and correct errors on the basis of the error check code in data read from the dynamic random access memory..Iaddend.