Electrostatic discharge protection circuit for semiconductor device

Abstract

An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.

We claim: 
     
       1. An ESD protection structure for a MOS device having a bonding pad and a . .P-.!. substrate, comprising: a symmetrical . .elongated.!. bi-polar transistor fabricated on and in the . .P-.!. substrate, the bi-polar transistor comprising an electrically floating . .elongated.!. base region having a width . .less than two.!. .Iadd.of 0.7 .Iaddend.microns;   a first . .N+.!. semiconductor region formed in the substrate adjacent to a first edge margin of the . .elongated.!. base region;   a first . .N-.!. well having a depth . .greater than two.!. .Iadd.of 3.7 .Iaddend.microns formed in the first . .N+.!. semiconductor region;   a second . .N+.!. semiconductor region formed in the substrate adjacent to a second edge margin of the . .elongated.!. base region;   a second . .N-.!. well having a depth . .greater than two.!. .Iadd.of 3.7 .Iaddend.microns formed in the second . .N+.!. semiconductor region;   the first . .N-.!. well electrically connected to an internal circuit of the MOS device and . .at a plurality of points.!. to the bonding pad; and   the second . .N-.!. well electrically connected . .at a plurality of points.!. to a ground line,   whereby, upon receipt of an ESD pulse, the ESD protection structure undergoes an avalanche breakdown that effectively conducts the ESD pulse between the bonding pad and the ground line and away from the internal circuit.   
     
     
       2. The structure of claim 1 in which the ground line is electrically connected to any one of a reference ground, the . .P-.!. substrate, a power supply voltage, and an ESD drain potential. 
     
     
       3. The structure of claim 1 in which the electrically floating . .elongated.!. base region comprises a depletion region located in the substrate and under a field oxide grown on the substrate. . .4. The structure of claim 1 in which the base region width is less than about one micron..!.. .5. The structure of claim 1 in which the first and second N+ regions each have a width greater than about four microns..!.. .6. The structure of claim 1 in which the depth of the first and second N- wells 
     
     
        is greater than about three microns..!.7. The structure of claim 1 in which the first . .N+.!. semiconductor region functions as a collector and the second . .N+.!. semiconductor region functions as an emitter of the 
     
     
        . .symmetrical elongated.!. bi-polar transistor. 8. The structure of claim 1 in which the first and second . .N-.!. wells each form . .N-.!. trenches in the . .P-.!. substrate, and in which the . .plurality of.!. electrical . .connection points on.!. .Iadd.connections to .Iaddend.each of the . .N-.!. wells are formed by a linearly distributed set of . .metal.!. contacts deposited on an elongated surface of each of the . .N-.!. wells. 
     
     
         . The structure of claim 1 in which the ESD pulse conforms to one of a 
     
     
        human model and a machine model of an electrical discharge pulse. 10. The structure of claim 3 in which the field oxide has a thickness of . ˜!. 0.4 microns. .Iadd.11. An ESD protection structure for a MOS device having a bonding pad and a substrate, comprising: a symmetrical bi-polar transistor fabricated on and in the substrate, the bi-polar transistor comprising an electrically floating base region having a width of about 0.7 microns;   a first semiconductor region formed in the substrate adjacent to a first edge margin of the base region;   a first well formed in the first semiconductor region;   a second semiconductor region formed in the substrate adjacent to a second edge margin of the base region;   a second well formed in the second semiconductor region;   the first well electrically connected to an internal circuit of the MOS device and to the bonding pad; and   the second well electrically connected to a ground line,   whereby, upon receipt of an ESD pulse, the ESD protection structure undergoes an avalanche breakdown that effectively conducts the ESD pulse between the bonding pad and the ground line and away from the internal circuit..Iaddend..Iadd.12. The structure of claim 11 in which the ground line is electrically connected to any one of a reference ground, the substrate, a power supply voltage, and an ESD drain potential..Iaddend..Iadd.13. The structure of claim 11 in which the electrically floating base region comprises a depletion region located in the substrate and under a field oxide grown on the   
     
     
        substrate..Iaddend..Iadd.14.  The structure of claim 11 in which the base region width is 0.7 microns..Iaddend..Iadd.15. The structure of claim 11 in which the depth of the first and second wells is about 3.7 microns..Iaddend..Iadd.16. The structure of claim 11 in which the first semiconductor region functions as a collector and the second semiconductor region functions as an emitter of the bi-polar transistor..Iaddend..Iadd.17. The structure of claim 11 in which the first and second wells each form trenches in the substrate, and in which the electrical connections to each of the wells are formed by a linearly distributed set of contacts deposited on an elongated surface of each of the wells..Iaddend..Iadd.18. The structure of claim 11 in which the ESD pulse conforms to one of a human model and a machine model of an electrical discharge pulse..Iaddend..Iadd.19. The structure of claim 13 in which the field oxide has a thickness of about 0.4 
     
     
        microns..Iaddend..Iadd. 0.  An ESD protection structure for a semiconductor device having a bonding pad and a substrate, the ESD protection structure comprising: an electrically floating base region fabricated on and in the substrate and including a depletion region located in the substrate for conducting ESD pulses by avalanche breakdown, the width of the base region being adapted to enhance a current gain of the protection structure so the ESD pulses may be conducted substantially non-destructively;   first and second semiconductor regions formed in the substrate symmetrically about the base region and adjacent to respective first and second edge margins of the base region; and   first and second wells formed in the respective first and second semiconductor regions and having depths greater than depths of the respective first and second semiconductor regions, the first well being coupled to an internal circuit of the semiconductor device and to the bonding pad, and the second well being coupled to a ground line,   whereby, upon receipt of the ESD pulses, the ESD protection structure effectively conducts the ESD pulses between the bonding pad and the ground   
     
     
        line and away from the internal circuit..Iaddend..Iadd.21.  The structure of claim 20 in which the ground line is electrically connected to any one of a reference ground, the substrate, a power supply voltage, and an ESD drain potential..Iaddend..Iadd.22. The structure of claim 20 in which the depletion region is located in the substrate under a field oxide grown on the substrate..Iaddend..Iadd.23. The structure of claim 20 in which the base region width is 0.7 microns..Iaddend..Iadd.24. The structure of claim 20 in which the depth of the first and second wells is 3.7 microns..Iaddend..Iadd.25. The structure of claim 20 in which the first semiconductor region functions as a collector and the second semiconductor region functions as an emitter..Iaddend..Iadd.26. The structure of claim 20 in which the first and second wells each form trenches in the substrate, and in which the electrical connections to each of the wells are formed by a linearly distributed set of contacts deposited on an elongated surface of each of the wells..Iaddend..Iadd.27. The structure of claim 20 in which the ESD pulses conform to one of a human model and a machine model of an electrical discharge pulse..Iaddend..Iadd.28. The structure of claim 22 in which the field oxide has a thickness of 0.4 microns..Iaddend.