Method and a device for synchronizing a signal

Abstract

A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator. The device also includes circuitry for decrementing the first number when the latest stored logic states of the phase comparator have a single occurrence of the first logic state and for incrementing the second number when the latest stored logic states of the phase comparator have a single occurrence of the second state.

What is claimed is: 
     
       1. A method of synchronizing an internal signal with a reference signal, comprising the steps of: a) providing a phase comparison signal having a first logic state when the phase of the internal signal is in advance with respect to the reference signal, and having a second logic state otherwise;   b) producing the internal signal by .Iadd.frequency .Iaddend.dividing a clock signal by a first variable divisor when said phase comparison signal is in said first logic state or a second variable divisor when said phase comparison signal is in said second logic state, the value of said first divisor initially being greater than the value of said second divisor; and   c) altering the . .value.!. .Iadd.values .Iaddend.of said first and second variable divisors based on the . .value.!. .Iadd.values .Iaddend.of successive states of said phase comparison signal.   
     
     
       2. The method of claim 1, further including the step of storing a predetermined number of successive states of said phase comparison signal. 
     
     
       3. The method of claim 2 wherein the step of altering the . .value.!. .Iadd.values .Iaddend.of said first and second variable divisors alters the . .value.!. .Iadd.values .Iaddend.by selectively incrementing or decrementing the value of said first or second variable divisor based on the . .value.!. .Iadd.values .Iaddend.of said predetermined number of successive states. 
     
     
       4. The method of claim 3, further including the step of preventing the value of said second .Iadd.variable .Iaddend.divisor from exceeding the value of said first .Iadd.variable .Iaddend.divisor by comparing the value of said first .Iadd.variable .Iaddend.divisor with the value of said second .Iadd.variable .Iaddend.divisor and disabling the decrementing of the value of said first .Iadd.variable .Iaddend.divisor and the incrementing of the value of said second .Iadd.variable .Iaddend.divisor when the value of said first .Iadd.variable .Iaddend.divisor equals the value of said second .Iadd.variable .Iaddend.divisor. 
     
     
       5. The method of claim 3, further including the step of preventing the value of said first .Iadd.variable .Iaddend.divisor from exceeding a predetermined maximum first divisor value by comparing the value of said first .Iadd.variable .Iaddend.divisor with . .the value of.!. said maximum first divisor .Iadd.value .Iaddend.and disabling the incrementing of the value of said first .Iadd.variable .Iaddend.divisor when the value of said first .Iadd.variable .Iaddend.divisor equals . .the value of.!. said maximum first divisor .Iadd.value.Iaddend.. 
     
     
       6. The method of claim 3, further including the step of preventing the value of said second .Iadd.variable .Iaddend.divisor from falling below a predetermined minimum second divisor value by comparing the value of said second .Iadd.variable .Iaddend.divisor with . .the value of.!. said minimum second divisor .Iadd.value .Iaddend.and disabling the decrementing of the value of said second .Iadd.variable .Iaddend.divisor when the value of said second .Iadd.variable .Iaddend.divisor equals . .the value of.!. said minimum second divisor .Iadd.value.Iaddend.. 
     
     
       7. A method for synchronizing an internal signal with respect to a reference signal having a reference period, said internal signal having a long period or a short period between which said reference period is normally included, comprising the following steps: a) analyzing the duration of the reference period with respect to the durations of the long and short periods;   b) when the reference period is closer to the long period than the short period, incrementing the short period;   c) when the reference period is closer to the short period than the long period, decrementing the long period;   d) when the reference period is higher than the long period, incrementing the long period; and   e) when the reference period is lower than the short period, decrementing the short period.   
     
     
       8. A method according to claim 7, wherein step a) consists in analyzing a predetermined number of the latest successive differences of phase between the internal signal and the reference signal and wherein the requirements of steps b) to e) are met when, respectively: the number of phases .Iadd.where the internal signal is .Iaddend.in advance is higher than the number of . .lagged.!. phases .Iadd.where the internal signal is lagging.Iaddend.;   the number of . .lagged.!. phases .Iadd.where the internal signal is lagging .Iaddend.is higher than the number of phases .Iadd.where the internal signal is .Iaddend.in advance;   there is no phase lag .Iadd.of the internal signal.Iaddend.; and   there is no phase advance .Iadd.of the internal signal.Iaddend..   
     
     
       9. A method according to claim 8, .Iadd.further .Iaddend.comprising the following steps: when the number of successive phases in advance is higher than a predetermined number, incrementing the long period; and   when the number of successive phase lags is higher than the predetermined number, decrementing the short period.   
     
     
       10. A method according to claim 7, .Iadd.further .Iaddend.comprising the following steps: comparing the long and short periods; and   inhibiting the decrementation of the long period and the incrementation of the short period when the difference between these periods is lower than a predetermined threshold.   
     
     
       11. A method according to claim 7, .Iadd.further .Iaddend.comprising the following steps: comparing the long period with a maximum period and inhibiting the incrementation of the long period when said periods are equal; and   comparing the short period with a minimum period and inhibiting the decrementation of the short period when said periods are equal.   
     
     
       12. A device for synchronizing an internal signal with a reference signal, the device comprising: a phase comparator providing a phase comparison signal with a first logic state when the phase of the internal signal is in advance with respect to the reference signal, and a second logic state otherwise;   a programmable frequency divider producing the internal signal by dividing a clock signal by a first variable divisor when said phase comparison signal is in said first logic state or a second variable divisor when said phase comparison signal is in said second logic state, the value of said first divisor initially being greater than the value of said second divisor; and   control means for altering the . .value.!. .Iadd.values .Iaddend.of said first and second variable . .divisor.!. .Iadd.divisors based on the values of successive states of said phase comparison signal.Iaddend..   
     
     
       13. The device of claim 12, further including storage means for storing a predetermined number of successive states of said phase comparison signal. 
     
     
       14. The device of claim 13 wherein said control means alters the . .value.!. .Iadd.values .Iaddend.of said first and second variable . .divisor.!. .Iadd.divisors .Iaddend.by selectively incrementing or decrementing the value of said first or second variable divisor based on the . .value.!. .Iadd.values .Iaddend.of said predetermined number of successive states. 
     
     
       15. The device of claim 14, further including means for preventing the value of said second .Iadd.variable .Iaddend.divisor from exceeding the value of said first .Iadd.variable .Iaddend.divisor by comparing the value of said first .Iadd.variable .Iaddend.divisor with the value of said second .Iadd.variable .Iaddend.divisor and disabling the portion of said control means for decrementing the value of said first .Iadd.variable .Iaddend.divisor and incrementing the value of said second .Iadd.variable .Iaddend.divisor when the value of said first .Iadd.variable .Iaddend.divisor equals the value of said second .Iadd.variable .Iaddend.divisor. 
     
     
       16. The device of claim 14, further including means for preventing the value of said first .Iadd.variable .Iaddend.divisor from exceeding a predetermined maximum first divisor value by comparing the value of said first .Iadd.variable .Iaddend.divisor with . .the value of.!. said maximum first divisor .Iadd.value .Iaddend.and disabling the portion of said control means for incrementing the value of said first .Iadd.variable .Iaddend.divisor when the value of said first .Iadd.variable .Iaddend.divisor equals . .the value of.!. said maximum first divisor .Iadd.value.Iaddend.. 
     
     
       17. The device of claim 14, further including means for preventing the value of said second .Iadd.variable .Iaddend.divisor from falling below a predetermined minimum second divisor value by comparing the value of said second .Iadd.variable .Iaddend.divisor with . .the value of.!. said minimum second divisor .Iadd.value .Iaddend.and disabling the portion of said control means for decrementing the value of said second .Iadd.variable .Iaddend.divisor when the value of said second .Iadd.variable .Iaddend.divisor equals . .the value of.!. said minimum second divisor .Iadd.value.Iaddend.. 
     
     
       18. A device for synchronizing an internal signal with respect to a reference signal, said signals each comprising pulses normally occurring at a rated frequency, comprising: a phase comparator providing a phase comparison signal at a predetermined logic state when the phase of said internal signal is in advance with respect to the phase of . .the synchronization.!. .Iadd.said reference .Iaddend.signal, and at a complementary logic state otherwise;   a programmable frequency divider fed by a clock and providing said internal signal;   a multiplexer providing to said divider, in order to program it, a high binary number when said phase comparison signal is at said predetermined state, and a low binary number, otherwise;   a means for sequentially storing a predetermined number of the latest states of said phase comparison signal;   a first counting means clocked by said internal signal and providing said high binary number to said multiplexer;   a first detection means setting said first counting means in down-counting position when said predetermined number of latest stored states of said phase comparison signal have a single state at said predetermined state;   a second counting means, clocked by said internal signal and providing said low binary number to said multiplexer; and   a second detection means setting said second counting means in up-counting position when said predetermined number of latest stored states of said phase comparison signal have a single state at said complementary state.   
     
     
       19. A device according to claim 18, further including: a third detection means setting said first counting means in up-counting position when said predetermined number of latest stored states of said phase comparison signal are all at said predetermined state; and   a fourth detection means setting said second counting means to down-counting position when said predetermined number of latest stored states of said phase comparison signal are at said complementary state.   
     
     
       20. A device according to claim 19, .Iadd.further .Iaddend.comprising a first comparator for comparing the high and low binary numbers and setting said first and second counting means in a standby state when the high binary number is lower than or equal to the low .Iadd.binary .Iaddend.number. 
     
     
       21. A device according to claim 18, .Iadd.further .Iaddend.comprising: a . .second.!. .Iadd.first .Iaddend.comparator comparing said high binary number with a maximum . .binary.!. number and setting said first counting means in a standby state when said maximum number is exceeded; and   a . .third.!. .Iadd.second .Iaddend.comparator comparing said low binary number with a minimum number and setting said second counting means in said standby state when said .Iadd.low binary number is less than said .Iaddend.minimum number . .is exceeded.!..   
     
     
       22. A device according to claim 18, wherein said programmable divider comprises a divider by two distinct numbers, either one . .is.!. .Iadd.being .Iaddend.selected by the output signal of a pulse generator programmed by the number provided by said multiplexer. .Iadd.23. A phase-locked loop, comprising: a phase comparator having a reference-signal input, a synchronized-signal input, and a phase output;   a shift register having a clock input, a signal input coupled to said phase output of said phase comparator, and a plurality of register outputs;   a programmable frequency-divider circuit having first and second divisor inputs, a control input coupled to said phase output of said phase comparator, and a synchronized-signal output that is coupled to said synchronized-signal input of said phase comparator;   a high-divisor counter having a clock input coupled to said synchronized-signal output of said phase comparator, a count-down input, and a high-count output coupled to said first divisor input of said frequency-divider circuit;   a low-divisor counter having a clock input coupled to said synchronized-signal output of said phase comparator, a count-up input, and a low-count output coupled to said second divisor input of said frequency-divider circuit;   a first logic circuit having a plurality of inputs, one of said inputs coupled to said phase output of said phase comparator and the remaining of said inputs each coupled to a corresponding one of said register outputs, said first logic circuit having an output coupled to said count-down input of said high-divisor counter; and   a second logic circuit having a plurality of inputs, one of said inputs coupled to said phase output of said phase comparator and the remaining of said inputs each coupled to a corresponding one of said register outputs, said second logic circuit having an output coupled to said count-up input of said low-divisor counter. .Iaddend..Iadd.24. The phase-locked loop of claim 23 wherein said first and second logic circuits each comprises an AND gate. .Iaddend..Iadd.25. The phase-locked loop of claim 23 wherein:   said first logic circuit comprises a first AND gate that has an inverting input for every other input, the number of inverting inputs greater than or equal to the number of noninverting inputs; and   said second logic circuit comprises a second AND gate that has an inverting input for every other input, the number of noninverting inputs of the second AND gate greater than or equal to the number of inverting inputs of   
     
     
        the second AND gate. .Iaddend..Iadd.26.  A phase-locked loop, comprising: a phase comparator having a reference-signal input, a synchronized-signal input, and a phase output;   a shift register having a clock input, a signal input coupled to said phase output of said phase comparator, and a plurality of register outputs;   a programmable frequency-divider circuit having first and second divisor inputs, a control input coupled to said phase output of said phase comparator, and a synchronized-signal output that is coupled to said synchronized-signal input of said phase comparator;   a high-divisor counter having a clock input coupled to said synchronized-signal output of said phase comparator, a count-up input, and a high-count output coupled to said first divisor input of said frequency-divider circuit;   a low-divisor counter having a clock input coupled to said synchronized-signal output of said phase comparator, a count-down input, and a low-count output coupled to said second divisor input of said frequency-divider circuit;   a first logic circuit having a plurality of inputs, one of said inputs coupled to said phase output of said phase comparator and the remaining of said inputs each coupled to a corresponding one of said register outputs, said first logic circuit having an output coupled to said count-up input of said high-divisor counter; and   a second logic circuit having a plurality of inputs, one of said inputs coupled to said phase output of said phase comparator and the remaining of said inputs each coupled to a corresponding one of said register outputs, said second logic circuit having an output coupled to said count-down   
     
     
        input of said low-divisor counter. .Iaddend..Iadd.27.  The phase-locked loop of claim 26 wherein said first and second logic circuits each comprises an AND gate. .Iaddend..Iadd.28. A phase-locked loop, comprising: a phase comparator having a reference-signal input, a synchronized-signal input, and a phase output;   a shift register having a clock input, a signal input coupled to said phase output of said phase comparator, and a plurality of register outputs;   a programmable frequency-divider circuit having a clock input, first and second divisor inputs, a control input coupled to said phase output of said phase comparator, and a synchronized-signal output that is coupled to said synchronized-signal input of said phase comparator;   a high-divisor counter having a clock input coupled to said synchronized-signal output of said phase comparator, a count-down input, a count-up input, and a high-count output coupled to said first divisor input of said frequency-divider circuit;   a low-divisor counter having a clock input coupled to said synchronized-signal output of said phase comparator, a count-down input, a count-up input, and a low-count output coupled to said second divisor input of said frequency-divider circuit;   a first logic circuit having a plurality of inputs, one of said inputs coupled to said phase output of said phase comparator and the remaining of said inputs each coupled to a corresponding one of said register outputs, said first logic circuit having an output coupled to said count-up input of said high-divisor counter;   a second logic circuit having a plurality of inputs, one of said inputs coupled to said phase output of said phase comparator and the remaining of said inputs each coupled to a corresponding one of said register outputs, said second logic circuit having an output coupled to said count-down input of said high-divisor counter;   a third logic circuit having a plurality of inputs, one of said inputs coupled to said phase output of said phase comparator and the remaining of said inputs each coupled to a corresponding one of said register outputs, said third logic circuit having an output coupled to said count-up input of said low-divisor counter; and   a fourth logic circuit having a plurality of inputs, one of said inputs coupled to said phase output of said phase comparator and the remaining of said inputs each coupled to a corresponding one of said register outputs, said fourth logic circuit having an output coupled to said count-down input of said low-divisor counter. .Iaddend..Iadd.29. The phase-locked loop of claim 28 wherein said shift register comprises three storage cells. .Iaddend..Iadd.30. The phase-locked loop of claim 28 wherein said programmable frequency-divider circuit comprises:   a programmable frequency divider having a clock input coupled to said clock input of said frequency-divider circuit, a divisor input, and a synchronized-signal output that is coupled to said synchronized-signal output of said frequency-divider circuit; and   a multiplexer having first, second, and control inputs respectively coupled to said first, second, and control inputs of said frequency-divider circuit, said multiplexer having an output coupled to said divisor input   
     
     
        of said programmable frequency divider. .Iaddend..Iadd.31.  The phase-locked loop of claim 28 wherein: said shift register has first second, and third register outputs and has three sequentially arranged memory cells each having an output that is coupled to a corresponding one said register outputs;   said first logic circuit comprises an AND gate having a first input coupled to said phase output of said phase comparator and having second, third, and fourth inputs respectively coupled to said first, second, and third register outputs;   said second logic circuit comprises an AND gate having a first terminal coupled to said phase output of said phase comparator, a second input coupled to said first register output, and a third input coupled to said second register output, said second terminal inverted with respect to said first and third terminals;   said third logic circuit comprises an AND gate having a first terminal coupled to said phase output of said phase comparator, a second input coupled to said first register output, and a third input coupled to said second register output, said first and third terminals inverted with respect to said second terminal; and   said fourth logic circuit comprises an AND gate having a first input coupled to said phase output of said phase comparator and having second, third, and fourth inputs respectively coupled to said first, second, and third register outputs, said inputs of said fourth logic circuit logically inverted with respect to said inputs of said first logic circuit. .Iaddend..Iadd.32. The phase-locked loop of claim 28, further comprising:   a first disable circuit intercoupled between said high-divisor counter and said first logic circuit, said first disable circuit having an input coupled to said output of said first logic circuit, a disable input, and an output coupled to said count-up terminal of said high-divisor counter;   a second disable circuit intercoupled between said high-divisor counter and said second logic circuit, said second disable circuit having an input coupled to said output of said second logic circuit, a disable input, and an output coupled to said count-down terminal of said high-divisor counter;   a third disable circuit intercoupled between said low-divisor counter and said third logic circuit, said third disable circuit having an input coupled to said output of said third logic circuit, a disable input, and an output coupled to said count-up terminal of said low-divisor counter;   a fourth disable circuit intercoupled between said low-divisor counter and said fourth logic circuit, said fourth disable circuit having an input coupled to said output of said fourth logic circuit, a disable input, and an output coupled to said count-down terminal of said low-divisor counter;   a first comparator having a high-divisor input coupled to said output of said high-divisor counter, a maximum-high-divisor input, and an output coupled to said disable input of said first disable circuit;   a second comparator having a high-divisor input coupled to said output of said high-divisor counter, a low-divisor input coupled to said output of said low-divisor, and an output coupled to said disable inputs of said second and third disable circuits; and   a third comparator having a low-divisor input coupled to said output of said low-divisor counter, a minimum-low-divisor input, and an output coupled to said disable input of said fourth disable circuit. .Iaddend..Iadd.33. The phase-locked loop of claim 28 wherein said programmable frequency-divider circuit comprises:   a selectable-divisor frequency divider having a clock input coupled to said clock input of said programmable frequency-divider circuit, a divisor input, and a signal output;   a multiplexer having first, second, and control inputs respectively coupled to said first divisor, second divisor, and control inputs of said programmable frequency-divider circuit, said multiplexer having an output;   a fixed frequency divider having an input coupled to said signal output of said selectable-divisor frequency divider, and having a synchronized-signal output coupled to said synchronized-signal output of said programmable frequency-divider circuit; and   a programmable pulse generator having an input coupled to said output of said multiplexer, an output coupled to said divisor input of said selectable-divisor frequency divider, and a clock input coupled to said signal output of said selectable-divisor frequency divider. .Iaddend..Iadd.34. A method, comprising:   performing a number of sequential comparisons between the phase of a reference signal having a reference period and the phase of a synchronized signal that has first and second periods;   causing said synchronized signal to have said first period if said reference signal lags said synchronized signal during a first of said comparisons;   lengthening said first period if said reference signal lags said synchronized signal during said first comparison and during a first predetermined number of comparisons that immediately precede said first comparison;   shortening said first period if said phase of said reference signal alternates leading and lagging said phase of said synchronized signal according to a first predetermined sequence during said first comparison and during a second predetermined number of comparisons that immediately precede said first comparison;   causing said synchronized signal to have said second period if said reference signal leads said synchronized signal during said first comparison;   shortening said second period if said reference signal leads said synchronized signal during said first comparison and during a third predetermined number of comparisons that immediately precede said first comparison; and   lengthening said second period if said phase of said reference signal alternates leading and lagging said phase of said synchronized signal according to a second predetermined sequence during said first comparison and during a fourth predetermined number of comparisons that immediately   
     
     
        precede said first comparison. .Iaddend..Iadd.35.  The method of claim 34, further comprising: inhibiting said lengthening of said first period if said first period is equal to or longer than a predetermined maximum period; and   inhibiting said shortening of said second period if said second period is equal to or shorter than a predetermined minimum period. .Iaddend..Iadd.36. The method of claim 34, further comprising:   comparing the lengths of said first and second periods; and   inhibiting said shortening of said first period and said lengthening of said second period if said second period is equal to or greater than said first period. .Iaddend..Iadd.37. The method of claim 34 wherein:   said first predetermined number equals said third predetermined number; and   said second predetermined number equals said fourth predetermined number. .Iaddend..Iadd.38. The method of claim 34 wherein:   said first and third predetermined numbers equal 3; and   said second and fourth predetermined numbers equal 2. .Iaddend..Iadd.39. The method of claim 34 wherein:   said first predetermined sequence equals lead-lag-lead of said phase of said reference signal with respect to said phase of said synchronized signal; and   said second predetermined sequence equals lag-lead-lag of said phase of said reference signal with respect to said phase of said synchronized   
     
     
        signal. .Iaddend..Iadd.40.  The method of claim 34, further comprising: generating said synchronized signal from a clock signal;   wherein said causing said synchronized signal to have said first period includes dividing said clock signal by a first divisor; and   said causing said synchronized signal to have said second period includes dividing said clock signal by a second divisor. .Iaddend..Iadd.41. The method of claim 34, further comprising:   generating said synchronized signal from a clock signal;   wherein said causing said synchronized signal to have said first period includes dividing said clock signal by a first divisor;   said causing said synchronized signal to have said second period includes dividing said clock signal by a second divisor;   wherein said lengthening said first period includes incrementing said first divisor;   wherein said shortening said first period includes decrementing said first divisor;   wherein said shortening said second period includes decrementing said second divisor; and   wherein said lengthening said second period includes incrementing said   
     
     
        second divisor. .Iaddend..Iadd.42.  The method of claim 34, further comprising: frequency dividing a clock signal by a first number to generate an intermediate signal;   frequency dividing said intermediate signal by a second number to generate said synchronized signal;   generating a first value for said first number in response to each of a third number of pulses of said intermediate signal; and   generating a second value for said first number in response to each of a fourth number of pulses of said intermediate signal, said fourth number being equal to the difference between a predetermined number and said   
     
     
        third number. .Iaddend..Iadd.43.  The method of claim 34, further comprising: frequency dividing a clock signal by a first number to generate an intermediate signal;   frequency dividing said intermediate signal by a second number to generate said synchronized signal;   generating a first value for said first number in response to each of a third number of pulses of said intermediate signal;   generating a second value for said first number in response to each of a fourth number of pulses of said intermediate signal, said fourth number being equal to the difference between a predetermined number and said third number;   wherein said causing said synchronized signal to have said first period includes generating a third value for said third number; and   wherein said causing said synchronized signal to have said second period includes generating a fourth value for said third number.   
     
     
        .Iaddend..Iadd.  .  The method of claim 34, further comprising: frequency dividing a clock signal by a first number to generate an intermediate signal;   frequency dividing said intermediate signal by 768 to generate said synchronized signal;   generating a third number that has a value that depends upon said phase of said reference signal with respect to said phase of said synchronized signal, said value ranging from 0 to 511;   setting said first number to 10 in response to each of said third number of pulses of said intermediate signal; and   setting said first number to 9 in response to each of a fourth number of pulses of said intermediate signal, said fourth number being equal to the difference between 1024 and said third number. .Iaddend.