Apparatus for reducing computer system power consumption

Abstract

A battery powered computer system monitors the address bus to determine when selected peripheral devices have not been accessed for a preset amount of time. When the preset amount of time has passed the system powers itself down and stops the system clock, placing it in a standby mode. The system is awakened by depressing a standby switch, unless there is insufficient energy in the batteries, under which circumstances an AC power source must be connected before the system can be awakened.

We claim: 
     
       1. An apparatus for use with a battery powered computer system for reducing power consumption of the battery powered computer system, the computer system including various circuitry, portions of which is clocked, the apparatus comprising: an address and data bus for communicating address and data information in the computer system;   a plurality of peripheral devices coupled to said address and data bus, said peripheral devices being accessed over said address and data bus by use of address values associated with each said peripheral device, each said peripheral device capable of being powered off;   means coupled to said address and data bus for accessing said peripheral devices by presenting address values associated with said particular peripheral device on said address and data bus;   means coupled to said address and data bus for analyzing the address values presented on said address bus by said means for accessing to determine if one of said peripheral devices is being accessed and producing a signal indicative thereof;   means coupled to said address value analyzing means and responsive to said address value analyzing means signal for timing an interval since any one of said peripheral devices has been accessed by said accessing means; and   means coupled to said timing means and said peripheral devices for powering off said peripheral devices when said interval exceeds a preset amount to enter a reduced power consumption state.   
     
     
       2. The apparatus of claim 1, further comprising: means coupled to portions of the circuitry for enabling power to said circuitry portions; and means coupled to said timing means and said enabling power means for disabling power to the coupled circuitry portions when said interval exceeds a preset amount.   
     
     
       3. The apparatus of claim 1, further comprising: system clock means for providing a system clock to the clocked portions of the circuitry included in the computer system; and   means coupled to said timing means and said system clock means for disabling the system clock to the circuitry portions when said interval exceeds a preset amount.   
     
     
       4. The apparatus of claim 1, further comprising: means for disabling said powering off means when the computer system is powered from an alternating current electrical source.   
     
     
       5. The apparatus of claim 1, further comprising: means for powering on said peripheral devices after they have been powered off by said powering off means.   
     
     
       6. The apparatus of claim 5, wherein said means for powering on includes a switch for activation by a user to indicate a desire to leave the reduced power consumption state. 
     
     
       7. The apparatus of claim 5, further comprising: means for monitoring the remaining battery energy; and   means coupled to said remaining battery energy monitoring means and said powering on means for disabling said means for powering on said peripheral devices when the remaining battery energy of the computer system is below a preset level.   
     
     
       8. The apparatus of claim 1, further comprising: means for disabling said powering off means when desired by a user.   
     
     
       9. The apparatus of claim 1, further comprising: means for initially disabling said powering off means;   means for allowing an operating system to take control of operations of the computer system;   means for interrupting operation of the computer system after the operating system has taken control; and   means responsive to said interrupt for enabling said powering off means when the controlling operating system allows response to said interrupt.   
     
     
       10. The apparatus of claim 1, further comprising: means for monitoring the remaining battery energy; and   means coupled to said remaining battery energy monitoring means and said powering off means for reducing the preset amount of said interval when the remaining battery energy of the computer system is below a first given level.   
     
     
       11. The apparatus of claim 10, further comprising: means coupled to said remaining battery energy monitoring means and said powering off means for further reducing the preset amount of said interval when the remaining battery energy is below a second given level, said second given level being less than said first given level.   
     
     
       12. The apparatus of claim 1, further comprising: means responsive to a signal from a user for reducing the preset amount of said interval.   
     
     
       13. The apparatus of claim 1, further comprising: means responsive to a command from a user for modifying the preset amount of said interval. .Iadd.14. A computer system adapted to switch between normal power consumption and reduced power consumption modes, comprising:   at least one peripheral device which draws, when the computer system is in a normal power consumption mode, an amount of power sufficient to support normal operation of said peripheral device when accessed by a peripheral device access address signal and which draws, when the computer system is in a reduced power consumption mode, a below normal or zero amount of power;   a central processing unit operable to generate the peripheral device access address signal;   a communication pathway connected with said central processing unit and said peripheral device for facilitating communication between said central processing unit and said peripheral device, said communication pathway including a bus connected with said central processing unit for receiving the peripheral device access address signal generated by said central processing unit; and   a power control circuit functionally separate from said peripheral device operable to cause said computer system to switch between a normal power consumption mode and a reduced power consumption mode by generating a power reducing control signal upon receipt of an elapsed time signal, said power control circuit including an access address detector connected with said bus operable to determine when said central processing unit has generated a peripheral device access address signal and to generate a timer reset signal in response thereto, and   a timer connected with said address detector to receive said timer reset signal, operable to determine the elapsed time since a timer reset signal was last received from said address detector, and to generate the elapsed time signal when the elapsed time exceeds a predetermined elapsed time limit,     whereby the computer system assumes a reduced power consumption mode as a result of said power control circuit generating said power reducing   
     
     
        control signal. .Iaddend..Iadd.15.  The system of claim 14, wherein said computer system is adapted to be connected with and receives power from a battery. .Iaddend..Iadd.16. The system of claim 15, further comprising means for adjusting said predetermined elapsed time limit when a voltage of said battery drops below a predetermined level. .Iaddend..Iadd.17. The system of claim 15, further comprising means for monitoring the remaining energy of said battery. .Iaddend..Iadd.18. The system of claim 14, wherein said computer system is adapted to be connected with and receives power from an AC power source. .Iaddend..Iadd.19. The system of claim 14, further comprising means for resetting said timer circuit when the computer system is powered up. .Iaddend..Iadd.20. The system of claim 14, further comprising means for disabling said power control circuit when said computer system is powered by an AC power source. .Iaddend..Iadd.21. The system of claim 20, further comprising means for reenabling said power control circuit when said computer system detects a change from being powered from an AC power source to a battery power source. 
     
     
        .Iaddend..Iadd. 2.  The system of claim 14, wherein said access address detector determines if said central processing unit has generated any one of a plurality of peripheral device access address signals corresponding, respectively, to a plurality of peripheral devices, and generates a timer reset signal in response thereto. .Iaddend..Iadd.23. The system of claim 14, further comprising a system clock source operable to provide a system clock signal to clocked portions of said computer system and a disabling circuit for disabling said system clock source when said elapsed time exceeds said predetermined elapsed time limit. .Iaddend..Iadd.24. The system of claim 14, further comprising a switch for activation by a user for disabling said power control circuit. .Iaddend..Iadd.25. The system of claim 14, further comprising means for modifying said predetermined elapsed time limit. .Iaddend..Iadd.26. The system of claim 14, wherein said timer is reset when said computer system is powered up. .Iaddend..Iadd.27. The system of claim 14, further comprising means for powering off portions of the circuitry of said computer system when the elapsed time exceeds said predetermined elapsed time limit. .Iaddend..Iadd.28. The system of claim 14, wherein said at least one peripheral device is one of a floppy disk drive, a keyboard, a modem, a hard disk drive, a serial communications device and a parallel communications device. .Iaddend..Iadd.29. The system of claim 14, wherein said timer comprises a countdown timer and said timer reset signal resets said countdown timer to a full count. .Iaddend..Iadd.30. The system of claim 14, wherein said power control circuit comprises decode logic. .Iaddend..Iadd.31. The system of claim 14, wherein the generation of said elapsed time signals is delayed in response to data transfer on said bus. .Iaddend..Iadd.32. The system of claim 14, further comprising means external to said power control circuit for increasing the power consumed by said peripheral device after the computer system is in a reduced power consumption mode. .Iaddend..Iadd.33. The system of claim 14, wherein said power control circuit is responsive to both said peripheral device addresses and to address qualifiers associated with said addresses. .Iaddend..Iadd.34. The system of claim 14, wherein the power control circuit causes the power consumed by said central processing unit to be reduced. .Iaddend..Iadd.35. A computer system adapted to switch between a normal power consumption mode and a reduced power consumption mode, comprising: at least one peripheral device which draws, when the computer system is in an operational power consumption mode, an amount of power sufficient to support functional operation of said peripheral device when accessed by a coded peripheral device address signal and which draws, when the computer system is in a reduced power consumption mode, a below normal or zero amount of power;   a central processing unit operable to generate the peripheral device access address signal;   a communication pathway connected with said central processing unit and said peripheral device for facilitating communication between said central processing unit and said peripheral device, said communication pathway including a bus connected with said central processing unit for receiving the coded peripheral device address signals generated by said central processing unit; and   a power control circuit functionally separate from said peripheral device operable to cause said computer system to switch between an operational power consumption mode and a reduced power consumption mode by generating a power reducing control signal upon receipt of an elapsed time signal, said power control circuit including an access address detector, in communication with said bus, to receive in un-decoded form the coded peripheral device address signal and to generate a timer reset signal in response thereto, and   a timer connected with said address detector to receive said timer reset signal, to determine the elapsed time since a timer signal was last received from said address detection circuit, and to generate the elapsed time signal when the elapsed time exceeds a predetermined elapsed time limit,     whereby the computer system assumes its reduced power consumption mode when said peripheral device is caused to draw a below normal or zero amount of   
     
     
        power. .Iaddend..Iadd.36.  The system of claim 35, wherein said computer system is adapted to be connected with and receives power from a battery. .Iaddend..Iadd.37. The system of claim 36, further comprising means for adjusting said predetermined elapsed time limit when a voltage of said battery drops below a predetermined level. .Iaddend..Iadd.38. The system of claim 36, further comprising means for monitoring the remaining energy of said battery. .Iaddend..Iadd.39. The system of claim 35, wherein said computer system is adapted to be connected with and receives power from an AC power source. .Iaddend..Iadd.40. The system of claim 35, further comprising means for resetting said timer when said computer system is 
     
     
        powered up. .Iaddend..Iadd.41.  The system of claim 35, further comprising means for disabling said power control circuit when said computer system is powered by an AC power source. .Iaddend..Iadd.42. The system of claim 41, further comprising means for reenabling said power control circuit when said computer system detects a change from being powered from an AC power source to a battery power source. .Iaddend..Iadd.43. The system of claim 35, wherein said access address detector determines if said central processing unit has generated any one of a plurality of coded peripheral device access address signals corresponding, respectively, to a plurality of peripheral devices, and generates a timer reset signal in response thereto. .Iaddend..Iadd.44. The system of claim 35, further comprising a system clock source to provide a system clock signal to clocked portions of said computer system and a disabling circuit for disabling said system clock source when said elapsed time exceeds said predetermined elapsed time limit. .Iaddend..Iadd.45. The system of claim 35, further comprising a switch for activation by a user for disabling said power control 
     
     
        circuit. .Iaddend..Iadd.46.  The system of claim 35, further comprising means for modifying said predetermined elapsed time limit. .Iaddend..Iadd.47. The system of claim 35, wherein said timer is reset when said computer system is powered up. .Iaddend..Iadd.48. The system of claim 35, further comprising means for powering off portions of the circuitry of said computer system when said elapsed time exceeds said predetermined elapsed time limit. .Iaddend..Iadd.49. The system of claim 35, wherein said at least one peripheral device is one of a floppy disk drive, a keyboard, a modem, a hard disk drive, a serial communications device and a parallel communications device. .Iaddend..Iadd.50. The system of claim 35, wherein said timer comprises a countdown timer and said timer reset signal resets said countdown timer to a full count. .Iaddend..Iadd.51. The system of claim 35, wherein said power control circuit comprises decode logic. .Iaddend..Iadd.52. The system of claim 35, wherein said power control circuit provides a notification signal to said central processing unit. .Iaddend..Iadd.53. An apparatus for reducing power consumption of a computer system having addressable peripheral devices, the system including address and data bus means for enabling communication of information in said computer system, and microprocessor means for accessing each of said peripheral devices by pressing its coded address on said address and data bus means, said apparatus for reducing power comprising: means for connection to individual ones of said peripheral devices for removing and/or reducing power to those peripheral devices;   power control means for centrally monitoring said address and data bus means, for centrally detecting in un-decoded form addressing of individual peripheral devices and for centrally producing a signal indicative thereof;   timing means responsive to said signal for establishing a timing interval each time addressing of at least one of said peripheral devices is detected; and   means, responsive to the established timing interval exceeding a preset amount, for operating the means for connection to individual peripheral devices for removing and/or reducing power to the peripheral devices, to cause said computer system to enter a reduced power consumption state.   
     
     
        .Iaddend..Iadd.54.  The apparatus according to claim 53, wherein said timing interval is established by a timer common to all the monitored peripheral devices and is reestablished consequent to each detected peripheral device addressing. .Iaddend..Iadd.55. The apparatus according to claim 53, wherein said timing interval is established or re-established by resetting a countdown time. .Iaddend..Iadd.56. The apparatus according to claim 53, further comprising means for reducing power consumed by said microprocessor when said timing interval exceeds the preset amount. .Iaddend..Iadd.57. The apparatus according to claim 53, wherein said power control means comprises an analyzer that produces a signal on detection of an address value presented on said address and data bus, and said timing interval is established or reestablished in response to said signal. .Iaddend..Iadd.58. The apparatus according to claim 57, wherein said microprocessor presents address values and address qualifiers to said address and data bus to access one of said peripheral devices and wherein said signal is produced in response to detection both an address value and an address qualifier. .Iaddend..Iadd.59. The apparatus according to claim 53, wherein said power control means is arranged to monitor addressing of a plurality of said peripheral devices, and wherein said means, responsive to the established timing interval exceeding a preset amount, is arranged to reduce power to at least one of said peripheral devices. .Iaddend..Iadd.60. The apparatus according to claim 53, wherein said power control means comprises decode logic. .Iaddend..Iadd.61. The apparatus according to claim 53, further comprising power connection to selected portions of said computer system and means to disable said power connection when said timing interval exceeds a preset amount. .Iaddend..Iadd.62. The apparatus according to claim 53, wherein said means, responsive to the established timing interval exceeding said preset amount, comprises peripheral device powering off means. .Iaddend..Iadd.63. The apparatus according to claim 62, further comprising means for powering on said peripheral devices powered off by said means responsive to the established timing interval exceeding said preset amount. 
     
     
        .Iaddend..Iadd.  .  The apparatus according to claim 63, wherein said means for powering on includes a user activated switch. .Iaddend..Iadd.65. The apparatus according to claim 63, further comprising means for disabling said means for powering on said peripheral devices when the remaining battery energy of a battery powered computer system is below a preset level. .Iaddend..Iadd.66. The apparatus according to claim 53, further comprising means for reducing the present amount of said interval when the remaining battery energy of a battery powered computer system is below a first predetermined level. .Iaddend..Iadd.67. The apparatus according to claim 66, further comprising means for further reducing the preset amount of said interval when the remaining battery energy is below a second predetermined level, less than said first predetermined level. .Iaddend..Iadd.68. The apparatus according to claim 53, further comprising means responsive to a signal from the user for modifying the preset amount of said interval. .Iaddend..Iadd.69. The apparatus according to claim 53, wherein said peripheral devices include one or more of a floppy disk drive, a keyboard, a modem, and a hard disk drive. .Iaddend..Iadd.70. The apparatus according to claim 53, wherein said power control means and said means for establishing a timing interval are external to said peripheral 
     
     
        devices. .Iaddend..Iadd.71.  A computer system according to claim 53, wherein said timing interval is initially established on powering up said computer system. .Iaddend..Iadd.72. A computer system according to claim 53, further comprising system clock means for providing a system clock to portions of the circuitry forming the computer system, and means for disabling the system clock to the circuitry portions when said timing interval exceeds a preset amount. .Iaddend..Iadd.73. A computer system according to claim 72, further comprising means operable to disable and to re-enable said means for establishing a timing interval. .Iaddend..Iadd.74. A computer system according to claim 53, wherein, when operated by AC power, said power control means is disabled. .Iaddend..Iadd.75. An apparatus for reducing power consumption of a computer system having addressable peripheral devices, the computer system including an address and data for enabling communication of information in said computer system, and a microprocessor for accessing each peripheral device by presenting its address on said address and data bus, said apparatus for reducing power consumption comprising: a centralized and functionally separate power control circuit for monitoring said address and data bus, for detecting addressing of individual peripheral devices and for producing a signal indicative of any such addressing, said power control circuit receiving address and/or data bus information as it is presented on said address and data bus by said microprocessor, said power control circuit including a timing circuit, responsive to said signal, for establishing a timing interval each time addressing of a peripheral device is detected; and   a power control effecting circuit, responsive to the established timing interval exceeding a preset amount, for removing and/or reducing power to the peripheral devices, to cause said computer system to enter a reduced     
     
     
        power consumption state. .Iaddend..Iadd.76.  A computing system comprising: a microprocessor providing addresses;   a bus coupled with said microprocessor for receiving addresses from said microprocessor and for communicating said received addresses;   at least one device peripheral to said microprocessor and coupled to said bus for receiving an address to access said peripheral device; and   a power control circuit functionally separate from said peripheral device for causing said computer system to switch between a normal power consumption mode and a reduced power consumption mode by generating the power reducing control signal upon receipt of an elapsed time signal, said power control circuit including an access address detection circuit connected with said bus for determining when said central processing unit has generated a peripheral device access address signal and for generating a timer reset signal in response thereto, and   a timer circuit connected with said address detection circuit for receiving said timer reset signal, for determining the elapsed time since a timer reset signal was last received from said address detection circuit, and for generating the elapsed time signal when the elapsed time exceeds a predetermined elapsed time limit,     whereby the computer system assumes a reduced power consumption mode as a result of said power control circuit generating said power reducing   
     
     
        control signal. .Iaddend..Iadd.77.  The computing system according to claim 76, wherein said power control circuit powers off said peripheral device. .Iaddend..Iadd.78. The computing system according to claim 76, further comprising: means for resetting said timing circuit when the computer system is powered up. .Iaddend..Iadd.79. The computing system according to claim 76, further comprising:   means for adjusting said predetermined elapsed time limit when the power source voltage of the computer system drops below a predetermined level. .Iaddend..Iadd.80. An apparatus for use with a computer system for reducing power consumption of the computer system, the computer system including various circuitry, portions of which are clocked, the apparatus comprising:   a central processing unit operable to generate peripheral device access address values;   an address and data bus coupled to said central processing unit for communicating address and data information in the computer system;   a plurality of peripheral devices coupled to said address and data bus, each said peripheral device being accessible over said address and data bus by use of an access address value associated with said peripheral device, each said peripheral device capable of being powered down; and   a power control circuit functionally separate from said peripheral devices for causing said computer system to switch between a normal power consumption mode and a reduced power consumption mode by generating a power reducing control signal and applying the power reducing control signal to cause said peripheral devices to power down upon receipt of an elapsed time signal, said power control circuit including an access value detection circuit, in communication with said address and data bus, for receiving said address value and for generating a timer reset signal in response thereto, and   a timer circuit connected with said address value detection circuit for receiving said timer reset signal, for determining the elapsed time since a timer signal was last received from said address value detection circuit, and for generating the elapsed time signal when the elapsed time     
     
     
        exceeds a predetermined elapsed time limit. .Iaddend..Iadd.81.  The apparatus according to claim 80, wherein the computer system is a battery 
     
     
        powered computer system. .Iaddend..Iadd.82.  The apparatus according to claim 81, wherein said predetermined elapsed time limit is based on the charge level of the battery of the computer system. .Iaddend..Iadd.83. The apparatus according to claim 82, wherein the computer system may receive power from an external AC source and further comprising: means coupled to said power control circuit for disabling said power control circuit when power is being received from the external AC source. .Iaddend..Iadd.84. The apparatus according to claim 83, further comprising:   means coupled to said power control circuit for reenabling said power control circuit when power is no longer being received from the AC source. .Iaddend..Iadd.85. The apparatus according to claim 81, wherein said power control circuit causes each of said peripheral devices to be powered down. .Iaddend..Iadd.86. The apparatus according to claim 81, further comprising:   means for starting said power control circuit when the computer system is powered up. .Iaddend..Iadd.87. The apparatus according to claim 81, further comprising:   means for adjusting said predetermined elapsed time limit. .Iaddend..Iadd.88. The apparatus according to claim 81, wherein at least one of said peripheral devices comprises one of a floppy disk drive, a keyboard, a modem, a hard disk drive, a serial communications device and a   
     
     
        parallel communications device. .Iaddend..Iadd.89.  A battery powered computer system comprising: an address and data bus for communicating address and data information in the computer system;   a plurality of peripheral devices coupled to said address and data bus, said peripheral devices being accessed over said address and data bus; and   a power control circuit functionally separate from said peripheral devices for causing said computer system to switch between a normal power consumption mode and a reduced power consumption mode by generating a power reducing control signal upon receipt of an elapsed time signal, said power control circuit including an access address detection circuit for determining when said central processing unit has generated a peripheral device access address signal and for generating a time reset signal in response thereto, and   a timer circuit connected with said address detection circuit for receiving said timer reset signal, for determining the elapsed time since a timer reset signal was last received from said address detection circuit, and for generating the elapsed time signal when the elapsed time exceeds a predetermined elapsed time limit,     whereby the computer system assumes a reduced power consumption mode as a result of said power control circuit generating said power reducing   
     
     
        control signal. .Iaddend..Iadd.90.  An apparatus for reducing power consumption of a computer system having addressable peripheral devices, the system including address and data bus means for enabling communication of information in said computer system, and microprocessor means for accessing each of said peripheral devices by presenting its coded address on said address and data bus means, said apparatus for reducing power comprising: controllable power supply paths to individual ones of said peripheral devices for removing and/or reducing power to those peripheral devices; p1 a power control circuit to centrally monitor said address and data bus means, for centrally detecting in un-decoded form addressing of individual peripheral devices and for centrally producing a signal indicative of the access of any one of said peripheral devices thereof, said power control circuit including: at least one timer responsive to said signal to establish a timing interval each time addressing of said one of said peripheral devices is detected; and   an operator, responsive to the established timing interval exceeding a preset amount, to operate the controllable power supply paths to individual peripheral devices to remove and/or reduce peripheral device power consumption, to cause said computer system to enter a reduced power consumption state. .Iaddend..Iadd.91. A computer system comprising:     a microprocessor;   at least one addressable device which draws, when the computer system is in a normal power consumption mode, an amount of power sufficient to support normal operation of said peripheral device and which draws, when the computer system is in a reduced power consumption mode, a below or zero amount of power;   a bus connected between said microprocessor and said device, said microprocessor operable to present on said bus an access address for said device;   address decode logic functionally separate from said device, said address device logic being responsive to the address for said device for generating an access signal;   means functionally separate from said device for commencing a timing interval of a defined period responsive to said access signal;   means functionally separate from said device and responsive to the reduction of the period remaining in said timing interval by a set time for reducing the power consumed by said device; and   means functionally separate from said device and responsive to the reduction of the period remaining in said timing interval by a set time for reducing the power consumed by said computer system. .Iaddend.