Circuit and method for erasing EEPROM memory arrays to prevent over-erased cells

Abstract

The device and process of this invention provide for eliminating reading errors caused by over-erased cells by applying flash erasing pulses, then flash programming pulses to the cells of an EEPROM array. The flash erasing pulses are sufficient in strength to over-erase the cells. The flash programming pulses applied to the control gates have the same voltages as those used to program individual cells. The strength of the programming electric field pulses adjacent the floating gates is controlled by applying a biasing voltage to one of the source/drain regions of the cells. The biasing voltage controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates to cause the threshold voltages of the cells to have positive values less than that of a predetermined wordline select voltage.

I claim: 
     
       1. A method for erasing a memory cell having at least one control terminal, a floating gate, a source terminal and a drain terminal, said memory cell programmable and erasable by applying electrical energy between said control terminal and at least one of said source and drain terminals to cause programming and erasing pulsed electric fields adjacent said floating gate, said memory cell readable using a preselected read voltage applied between said control terminal and at least one of said source terminal and said drain terminal, the method comprising: initially applying an erasing electrical energy pulse having a first energy-level between said control terminal and said at least one of said source and drain terminals of said cell; and   then applying a programing electrical energy pulse having a second energy-level between said control terminal and said at least one of said source and drain terminals of said cell;   wherein said first energy level of said erasing electrical energy pulse is sufficient to cause said cell to have a threshold voltage of opposite polarity to said preselected read voltage; and   wherein said second energy level of said programming electrical energy pulse is such that said cell has a threshold voltage of the same polarity as said read voltage but that is less than said read voltage.   
     
     
       2. The method of claim 1, wherein said programming electrical energy pulse causes a pulsed electric field directed away from said floating gate, and wherein said erasing electrical energy pulse causes a pulsed electric field directed toward said floating gate. 
     
     
       3. The method of claim 1, wherein said control terminal is connected to a wordline, wherein said source terminal is connected to a source-column line, wherein said drain terminal is connected to a drain-column line, and wherein said programming and erasing electrical energy pulses are caused by pulsed programming voltages and pulsed erasing voltages applied between said wordline and at least one of said source-column line and said drain-column line. 
     
     
       4. The method of claim 1, wherein said control terminal is connected to a wordline, wherein said source terminal is connected to a source-column line, wherein said drain terminal is connected to a drain-column line, wherein said programming and erasing electrical energy pulses are caused by pulsed programming voltages and pulsed erasing voltages applied between said wordline and at least one of said source-column line and said drain-column line; and wherein said second energy-level of said programming electrical energy pulse is controlled by applying a bias voltage to at least one of a said source-column line or a said drain-column line. 
     
     
       5. The method of claim 1, wherein said control terminal is connected to a wordline, wherein said source terminal is connected to a source-column line, wherein said drain terminal is connected to a drain-column line, wherein said second and first energy-levels of said programming and erasing electrical energy pulses are caused by pulsed programming currents and pulsed erasing currents applied between said wordline and at least one of said source-column line and said drain-column line. 
     
     
       6. The method of claim 1, wherein said control terminal is connected to a wordline, wherein said source terminal is connected to a source-column line, wherein said drain terminal is connected to a drain-column line, wherein said second and first energy-levels of said programming and erasing electrical energy pulses are related to the length of electrical programming and erasing pulses applied between said wordline and at least one of said source-column line and said drain-column line. 
     
     
       7. A non-volatile memory array, comprising: memory cells arranged in rows and columns, each said memory cell having a source-drain path between first and second terminals and having a control-gate terminal;   a source-column line connected to each said first terminal of each said memory cell in a said column;   a drain-column line connected to each said second terminal of each said memory cell in a said column;   a wordline connected to each said control-gate terminal of each said memory cell in a said row;   each said memory cell having a floating-gate conductor insulated from said source-drain path and from said control gate, said floating-gate conductor being programmable and erasable by programming and erasing electrical energy pulses applied between said control gate and at least one of said first and said second terminals;   a column decoder connected to said source-column lines and said drain-column lines and a wordline decoder connected to said wordlines for providing said programming and erasing electrical energy pulses to said memory cells via said wordlines and at least one of said source-column lines and said drain-column lines; and   an erase control circuit for causing said column decoder and said wordline decoder to provide said programming and erasing electrical energy pulses to said memory cells via said wordlines and at least one of said source-column lines and said drain-column lines, said control circuit causing said erasing electrical energy pulses having a sufficiently high energy-level to cause .Iadd.at least one of .Iaddend.said floating gates initially to be over-erased, said control circuit subsequently causing said column decoder and said wordline decoder to provide said programming electrical energy pulses to . .said cells.!. .Iadd.cell having said at least one of said floating gates .Iaddend.via said wordlines and at least one of said source-column lines and said drain-column lines.Iadd., such that said cell has a positive threshold voltage less than a predetermined positive wordline select voltage.Iaddend..   
     
     
       8. The array of claim 7, wherein said energy-level of said programming and erasing electrical energy pulses is controlled by varying voltages applied to said wordlines and at least one of said source-column lines and said drain-column lines. 
     
     
       9. The array of claim 7, wherein said column decoder also provides a predetermined bias voltage to at least one of said source-column lines and drain-column lines, wherein said erase control circuit also causes said bias voltage to be applied to at least one of said source-column lines and said drain-column lines, and wherein said predetermined bias voltage has a value that causes said cells to have positive threshold voltages less than a predetermined positive wordline select voltage. 
     
     
       10. The array of claim 7, wherein said energy-level of said programming and erasing electrical energy pulses is controlled by varying currents applied to said wordlines and at least one of said source-column lines and said drain-column lines. 
     
     
       11. The array of claim 7, wherein said energy-level of said programming and erasing electrical energy pulses is controlled by varying the length of electrical pulses applied to said wordlines and at least one of said source-column lines and said drain-column lines. 
     
     
       12. A method of erasing a memory-cell array prior to programming said array, each said memory cell including a floating gate, .Iadd.each said memory cell characterized by a positive read voltage, .Iaddend.the method comprising: initially applying erasing electrical energy pulses to said cells of said memory cell array, said erasing electrical energy pulses having a energy-level sufficient to cause . .each.!. .Iadd.at least one said .Iaddend.memory cell of said array to have a negative threshold voltage;   then applying programming electrical energy pulses to said cells of said memory cell array, said programming electrical energy pulses having an energy-level sufficient to cause . .each.!. .Iadd.said at least one .Iaddend.cell of said array to have a positive threshold voltage .Iadd.less than said read voltage of said array.Iaddend..   
     
     
       13. The method of claim 12, wherein said array includes a plurality of wordlines, source-column lines and drain-column lines; wherein each said memory cell has a terminal connected to a said wordline, has a terminal connected to a said source-column line, and has a terminal connected to a said drain-column line; wherein pulsed programming and erasing voltages are applied between said wordlines of said memory array and at least one of said source-column lines and said drain-column lines of said memory array electrical energy pulses. 
     
     
       14. The method of claim 12, wherein said array includes a plurality of wordlines, source-column lines and drain-column lines; wherein each said memory cell has a terminal connected to a said wordline, has a terminal connected to a said source-column line, and has a terminal connected to a said drain-column line; wherein pulsed programming and erasing currents are applied between said wordlines of said memory array and at least one of said source-column lines and said drain-column lines of said memory array to form said pulsed programming and erasing electrical energy pulses. 
     
     
       15. The method of claim 12, wherein said array includes a plurality of word lines, source-column lines and drain-column lines; wherein each said memory cell has a terminal connected to a said wordline, has a terminal connected to a said source-column line, and has a terminal connected to a said drain-column line; wherein variable-length programming and erasing electric pulses are applied between said wordlines of said memory array and at least one of said source-column lines and said drain-column lines of said memory array; and wherein said energy-level of said programming and erasing electrical energy pulses is related to the length of said variable-length programming and erasing electric pulses. 
     
     
       16. The method of claim 12, wherein said erasing electrical energy pulses cause pulsed electric fields directed toward said floating gates and wherein said programming electrical energy pulses cause pulsed electric fields directed away from said floating gates. .Iadd. 
     
     
       17.  A method for erasing a memory cell having at least one control terminal, a floating gate, a source terminal and a drain terminal, said memory cell programmable and erasable by applying electrical energy between said control terminal and at least one of said source and drain terminals to cause programming and erasing pulsed electric fields adjacent said floating gate, said memory cell readable using a preselected read voltage applied between said control terminal and at least one of said source terminal and said drain terminal, the method comprising: initially applying an erasing electrical energy pulse having a first energy-level between said control terminal and said at least one of said source and drain terminals of said cell; and   then applying a programming electrical energy pulse having a second energy-level between said control terminal and said at least one of said source and drain terminals of said cell;   wherein said first energy level of said erasing electrical energy pulse is sufficient to cause said cell to have a threshold voltage less than a first voltage; and   wherein said second energy level of said programming electrical energy pulse is such that said cell has a threshold voltage greater than said first voltage and less than said read voltage. .Iaddend..Iadd.18. The method of claim 17, wherein said first voltage is zero volts.   
     
     
        .Iaddend..Iadd.19.  A method for erasing a memory cell having at least one control terminal, a floating gate, a source terminal and a drain terminal, said memory cell programmable and erasable by applying electrical energy between said control terminal and at least one of said source and drain terminals to cause programming and erasing pulsed electric fields adjacent said floating gate, said memory cell readable using a preselected read voltage applied between said control terminal and at least one of said source terminal and said drain terminal, the method comprising: initially applying an erasing electrical energy pulse having a first energy-level between said control terminal and said at least one of said source and drain terminals of said cell; and   then applying a programming electrical energy pulse having a second energy-level between said control terminal and said at least one of said source and drain terminals of said cell;   wherein said first energy level of said erasing electrical energy pulse is sufficient to cause said cell to have a threshold voltage representing a more energetically erased condition than that of a first voltage, said first voltage representing an erased condition relative to the read voltage; and   wherein said second energy level of said programming electrical energy pulse is such that said cell has a threshold voltage between said first voltage and said read voltage. .Iaddend..Iadd.20. The method of claim 19,   
     
     
        wherein said first voltage is zero volts. .Iaddend..Iadd.21.  A method of erasing a floating-gate memory cell having a preselected read voltage, comprising the steps of: erasing the memory cell such that the cell has an initial threshold voltage less than a first voltage; and   programming the memory cell such that the cell has a final threshold voltage greater than the first voltage and less than the preselected read voltage. .Iaddend..Iadd.22. The method of claim 21, wherein the first   
     
     
        voltage is zero volts. .Iaddend..Iadd.23.  A method of erasing a floating-gate memory cell having a preselected read voltage, comprising the steps of: erasing the memory cell such that the cell has an initial threshold voltage representing a more energetically erased condition than that of a first voltage, said first voltage representing an erased condition relative to the read voltage; and   programming the memory cell such that the cell has a final threshold voltage between the first voltage and the preselected read voltage. .Iaddend..Iadd.24. The method of claim 23, wherein the first voltage is   
     
     
        zero volts. .Iaddend..Iadd.25.  A memory device readable using a preselected read voltage, comprising: a source;   a drain separated from said source by a source-drain path;   a control gate insulated from said source-drain path;   a floating gate insulated from said source-drain path and said control gate;   a column decoder coupled to said source and drain to apply programming and erasing voltages;   a wordline decoder coupled to said control gate to apply programming and erasing voltages to said control gate; and   an erase control circuit coupled to said column decoder and wordline decoder, said control circuit controlling said column decoder and wordline decoder initially to generate erasing voltages sufficient to result in an initial threshold voltage less than a first voltage, and subsequently to generate programming voltages sufficient to result in a final threshold voltage less than the read voltage. .Iaddend..Iadd.26. The memory device of claim 25, wherein said final threshold voltage resulting from said programming voltages is greater than said first voltage. .Iaddend..Iadd.27. The memory device of claim 26, wherein said first   
     
     
        voltage is zero volts. .Iaddend..Iadd.28.  A memory device readable using a preselected read voltage, comprising: a source;   a drain separated from said source by a source-drain path;   a control gate insulated from said source-drain path;   a floating gate insulated from said source-drain path and said control gate, said floating-gate being programmable and erasable by programming and erasing electrical energy pulses applied between said control gate and at least one of said source and drain;   a column decoder connected to said source and drain and a wordline decoder connected to said control gate to provide said programming and erasing electrical energy pulses; and   an erase control circuit operable to cause said column decoder and said wordline decoder to provide said programming and erasing electrical energy pulses, said control circuit causing said erasing electrical energy pulses to have a sufficiently high energy-level to result in an initial threshold voltage less than a first voltage, said control circuit subsequently causing said column decoder and said wordline decoder to provide said programming electrical energy pulses sufficient to result in a final threshold voltage less than the read voltage. .Iaddend..Iadd.29. The memory device of claim 28, wherein said final threshold voltage resulting from said programming electrical energy pulses is greater than said first voltage. .Iaddend..Iadd.30. The memory device of claim 29, wherein said   
     
     
        first voltage is zero volts. .Iaddend..Iadd.31.  A memory device readable using a preselected read voltage, comprising: a source;   a drain separated from said source by a source-drain path;   a control gate insulated from said source-drain path;   a floating gate insulated from said source-drain path and said control gate;   a first decoder coupled to said source and drain to apply programming and erasing voltages;   a second decoder coupled to said control gate to apply programming and erasing voltages to said control gate; and   an erase control circuit coupled to said column decoder and wordline decoder, said control circuit controlling said column decoder and wordline decoder initially to generate erasing voltages sufficient to result in an initial threshold voltage less than a first voltage, and subsequently to generate programming voltages sufficient to result in a final threshold voltage greater than said first voltage and less than the read voltage. .Iaddend..Iadd.32. The memory device of claim 31, wherein said first voltage is zero volts. .Iaddend.