Semiconductor memory device

Abstract

A semiconductor memory device is disclosed which comprises a regular row/column memory cell array having blocks obtained by dividing the memory cell array in the column and row directions, .Iadd.the blocks each being further divided in the column direction to form a plurality of sections, .Iaddend.a first peripheral circuit . .irregularly.!. provided between the blocks divided in the column direction, a second peripheral circuit provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit provided between the first peripheral circuit and the respective block and including a second decoder, and . .a fourth peripheral circuit provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit.!. .Iadd.sense amplifiers provided between neighboring sections in each of the blocks.Iaddend..

What is claimed is: 
     
       1. A semiconductor memory device comprising: a regular row/column memory cell array having four blocks obtained by dividing the memory cell array in the column and row directions.Iadd., wherein said four blocks are each divided in the column direction to form a plurality of sections.Iaddend.;   a first peripheral circuit provided between the blocks divided in the column direction of the regular row/column memory cell array.Iadd., wherein each of said sections further includes a bit line extending in the column direction and each of said blocks includes a column select line extending parallel to said bit lines and across the sections.Iaddend.;   a second peripheral circuit provided between adjacent blocks divided in the row direction of the regular row/column .Iadd.memory .Iaddend.cell array and including a first decoder.Iadd., wherein each of said sections includes a word line extending in the row direction and coupled to said second peripheral circuit.Iaddend.;   a third peripheral circuit provided in the column direction between the first peripheral circuit and the respective adjacent block and including a second decoder; and   . .a fourth peripheral circuit provided at an outer marginal portion of the memory cell array and including bonding pads and input protection circuit.!.   .Iadd.sense amplifiers provided between neighboring sections in each of said four blocks.Iaddend..   
     
     
       2. The semiconductor memory device according to claim 1, wherein . .the respective block in said regular row/column memory cell array.!. .Iadd.each of said four blocks .Iaddend.is divided . .by.!. .Iadd.into .Iaddend.2 n  (n: a natural number) . .into.!. sections, . .the.!. .Iadd.each .Iaddend.section constituting a minimal memory .Iadd.cell .Iaddend.array unit. 
     
     
       3. The semiconductor memory device according to claim 1, wherein said first decoder is shared by adjacent blocks in said memory cell array. 
     
     
       4. The semiconductor memory device according to claim 1, wherein said first decoder . .is composed of.!. .Iadd.comprises .Iaddend.a row decoder. 
     
     
       5. The semiconductor memory device according to claim 1, wherein said second decoder . .is composed of.!. .Iadd.comprises .Iaddend.a column decoder. 
     
     
       6. A semiconductor memory device comprising: a regular row/column memory cell array having eight blocks obtained by dividing the memory cell array in the column and row directions with four of the eight blocks being arranged in the . .column.!. .Iadd.row .Iaddend.direction.Iadd., wherein said eight blocks are each divided in the column direction to form a plurality of sections.Iaddend.;   a first peripheral circuit formed between the blocks divided in the column direction of the regular row/column memory cell array;   a second peripheral circuit provided between a respective pair of blocks divided in the row direction of the regular row/column .Iadd.memory .Iaddend.cell array and including a first decoder;   a third peripheral circuit provided in the column direction between the first peripheral circuit and the respective block and including a second decoder; and . .a fourth peripheral circuit provided at an outer marginal portion of the memory cell array, including an area between the adjacent pairs of blocks, said fourth peripheral circuit including bonding pads and input protection circuit.!.   sense amplifiers provided between neighboring sections in each of said eight blocks.   
     
     
       7. The semiconductor memory device according to claim 6, wherein . .a respective block in said memory cell array.!. .Iadd.each of said eight blocks .Iaddend.is divided . .by.!. .Iadd.into .Iaddend.2 n  (n: a natural number) . .into.!. sections, . .the.!. .Iadd.each .Iaddend.section constituting a minimal memory .Iadd.cell array .Iaddend.unit. 
     
     
       8. The semiconductor memory device according to claim 6, wherein said first decoder is shared by adjacent blocks in said memory cell array. 
     
     
       9. The semiconductor memory device according to claim 6, wherein said first decoder . .is composed of.!. .Iadd.comprises .Iaddend.a row decoder. 
     
     
       10. The semiconductor memory device according to claim 6, wherein said second decoder . .is composed of.!. .Iadd.comprises .Iaddend.a column decoder. 
     
     
       11. A semiconductor memory device comprising: a regular row/column memory cell array having an l×m number (l, m: a natural number) of blocks obtained by dividing the memory cell array in the column and row directions corresponding to l and m, respectively.Iadd., wherein said blocks are each divided in the column direction to form a plurality of sections.Iaddend.;   . .a.!. .Iadd.an irregular .Iaddend.first peripheral circuit provided . .in an irregular fashion.!. between the blocks divided in the column direction of the regular row/column memory cell array;   a second peripheral circuit provided between a respective pair of blocks divided in the row direction of the regular row/column .Iadd.memory .Iaddend.cell array and including a first decoder;   a third peripheral circuit provided in the column direction between the first peripheral circuit and the respective block and including a second decoder; . .and.!.   a fourth peripheral circuit provided at an outer marginal portion of the memory cell array, including an area between the adjacent pairs of blocks, . .and.!. .Iadd.said .Iaddend.fourth peripheral circuit . .and.!. including bonding pads and input protection . .circuit.!. .Iadd.circuitry; and   sense amplifiers provided between neighboring sections in said blocks.Iaddend..   
     
     
       12. A semiconductor memory device according to claim 11, wherein . .the respective block in said regular row/column memory cell array.!. .Iadd.each of said blocks .Iaddend.is divided . .by.!. .Iadd.into .Iaddend.2 n  (n: a natural number) . .into.!. sections, . .the.!. .Iadd.each .Iaddend.section constituting a minimal memory .Iadd.cell array .Iaddend.unit. 
     
     
       13. The semiconductor memory device according to claim 11, wherein said first decoder is shared by adjacent blocks in the memory .Iadd.cell .Iaddend.array. 
     
     
       14. The semiconductor memory device according to claim 11, wherein said first decoder . .is composed of.!. .Iadd.comprises .Iaddend.a row decoder. 
     
     
       15. The semiconductor memory device according to claim 11, wherein said second decoder . .is composed of.!. .Iadd.comprises .Iaddend.a column decoder. .Iadd.16. The semiconductor memory device according to claim 1, wherein each said column select line extends from said third peripheral circuit..Iaddend..Iadd.17. The semiconductor memory device according to claim 16, wherein said first decoder comprises a row decoder and said second decoder comprises a column decoder..Iaddend..Iadd.18. The semiconductor memory device according to claim 17, wherein said first peripheral circuit is provided between adjacent blocks divided in the column direction of the regular row/column memory cell 
     
     
        array..Iaddend..Iadd.19.  The semiconductor memory device according to claim 18, wherein said first peripheral circuit comprises a bus line extending in the row direction and coupled to said row decoder..Iaddend..Iadd.20. The semiconductor memory device according to claim 1, further comprising a fourth peripheral circuit provided at an outer margin of the regular row/column memory cell array, said fourth peripheral circuit comprising bonding pads and input protection circuitry..Iaddend..Iadd.21. The semiconductor memory device according to claim 1, further comprising gating circuits formed between neighboring sections of each of said four blocks..Iaddend..Iadd.22. The semiconductor memory device according to claim 21, wherein said regular row/column memory cell array, said first peripheral circuit, said second peripheral circuit, said third peripheral circuit, said sense amplifiers and said gating circuits are each formed on a single semiconductor 
     
     
        chip..Iaddend..Iadd.23.  The semiconductor memory device according to claim 6, wherein each of said sections further includes a bit line extending in the column direction..Iaddend..Iadd.24. The semiconductor memory device according to claim 23, wherein each of said sections includes a word line extending in the row direction and coupled to said second peripheral circuit..Iaddend..Iadd.25. The semiconductor memory device according to claim 24, wherein each of said blocks includes a column select line extending parallel to said bit lines..Iaddend..Iadd.26. The semiconductor memory device according to claim 25, wherein each said column select line extends across the sections in its respective block..Iaddend..Iadd.27. The semiconductor memory device according to claim 26, wherein each said column select line extends from said third peripheral circuit..Iaddend..Iadd.28. The semiconductor memory device according to claim 27, wherein said first decoder comprises a row decoder and said second decoder comprises a column decoder..Iaddend..Iadd.29. The semiconductor memory device according to claim 28, wherein said first peripheral circuit is provided between adjacent blocks divided in the column direction of the regular row/column memory cell array..Iaddend..Iadd.30. The semiconductor memory device according to claim 29, wherein said first peripheral circuit comprises a bus line extending in the row direction and coupled to said row 
     
     
        decoder..Iaddend..Iadd.31.  The semiconductor memory device according to claim 6, further comprising a fourth peripheral circuit provided at an outer margin of the regular row/column memory cell array including an area between the adjacent pair of blocks, said fourth peripheral circuit comprising bonding pads and input protection circuitry..Iaddend..Iadd.32. The semiconductor memory device according to claim 6, wherein each said block includes a column select line extending in the column direction..Iaddend..Iadd.33. The semiconductor memory device according to claim 32, wherein each said column select line extends across each of said sections in its respective block..Iaddend..Iadd.34. The semiconductor memory device according to claim 33, wherein each said section includes a word line extending in the row direction and coupled to said second peripheral circuit and a bit line extending in said column direction..Iaddend..Iadd.35. The semiconductor memory device according to claim 34, further comprising gating circuits formed between neighboring sections of each of said eight blocks..Iaddend..Iadd.36. The semiconductor memory device according to claim 35, wherein said regular row/column memory cell array, said first peripheral circuit, said second peripheral circuit, said third peripheral circuit, said sense amplifiers and said gating circuits are each formed on a single semiconductor chip..Iaddend..Iadd.37. The semiconductor memory device according to claim 11, wherein each of said sections further includes a bit line extending in 
     
     
        the column direction..Iaddend..Iadd.38.  The semiconductor memory device according to claim 37, wherein each of said sections includes a word line extending in the row direction and coupled to said second peripheral circuit..Iaddend..Iadd.39. The semiconductor memory device according to claim 38, wherein each of said blocks includes a column select line extending parallel to said bit lines..Iaddend..Iadd.40. The semiconductor memory device according to claim 39, wherein each said column select line extends across the sections in its respective block..Iaddend..Iadd.41. The semiconductor memory device according to claim 40, wherein each said column select line extends from said third peripheral circuit..Iaddend..Iadd.42. The semiconductor memory device according to claim 41, wherein said first decoder comprises a row decoder and said second decoder comprises a column decoder..Iaddend..Iadd.43. The semiconductor memory device according to claim 42, wherein said first peripheral circuit is provided between adjacent blocks divided in the column direction of the regular row/column memory cell array..Iaddend..Iadd.44. The semiconductor memory device according to claim 43, wherein said first peripheral circuit comprises a bus line extending in the row direction and coupled to said row 
     
     
        decoder..Iaddend..Iadd.45.  The semiconductor memory device according to claim 11, wherein each said block includes a column select line extending in the column direction..Iaddend..Iadd.46. The semiconductor memory device according to claim 45, wherein each said column select line extends across each of said sections in its respective block..Iaddend..Iadd.47. The semiconductor memory device according to claim 46, wherein each said section includes a word line extending in the row direction and coupled to said second peripheral circuit and a bit line extending in said column direction..Iaddend..Iadd.48. The semiconductor memory device according to claim 47, further comprising gating circuits formed between neighboring sections of each of said blocks..Iaddend..Iadd.49. The semiconductor memory device according to claim 48, wherein said regular row/column memory cell array, said first peripheral circuit, said second peripheral circuit, said third peripheral circuit, said sense amplifiers and said gating circuits are each formed on a single semiconductor chip..Iaddend..Iadd.50. A semiconductor memory device comprising: a memory cell array having four blocks obtained by dividing the memory cell array in a column direction and a row direction, each of said four blocks of the row/column memory cell array including a plurality of minimal memory cell array units, and each of said four blocks of the memory cell array including at least one sense amplifier arranged between neighboring minimal memory cell array units, each of said minimal memory cell array units including a word line extending in the row direction and connected to the memory cells, a bit line extending in the column direction and connected to the memory cells, and a column select line extending parallel to the bit line;   a first peripheral circuit provided between the blocks divided in the column direction of the memory cell array;   a second peripheral circuit provided between adjacent blocks divided in the row direction of the memory cell array and including a first decoder; and   a third peripheral circuit provided in the column direction between the first peripheral circuit and the respective adjacent block and including a second decoder..Iaddend..Iadd.51. The semiconductor memory device according to claim 50, wherein each of said four blocks of the memory cell array further includes a gating circuit arranged between the neighboring   
     
     
        minimal memory cell array units..Iaddend..Iadd.52.  The semiconductor memory device according to claim 50, wherein said column select line extends across a plurality of minimal memory cell array units..Iaddend..Iadd.53. The semiconductor memory device according to claim 50, wherein said first peripheral circuit includes a group of signal lines extending in the row direction..Iaddend..Iadd.54. The semiconductor memory device according to claim 53, wherein said group of signal lines is connected to said first decoder..Iaddend..Iadd.55. The semiconductor memory device according to claim 50, further comprising a fourth peripheral circuit provided at an outer marginal portion of the memory cell array and including bonding pads and an input protection circuit, wherein said bonding pads are arranged in a longitudinal direction of the memory cell array..Iaddend..Iadd.56. The semiconductor memory device according to claim 50, wherein said memory cells of the memory cell array are RAMS..Iaddend..Iadd.57. The semiconductor memory device according to claim 56, wherein said RAMs are dynamic RAMs..Iaddend..Iadd.58. The semiconductor memory device according to claim 56, wherein said RAMs are static RAMs..Iaddend..Iadd.59. A semiconductor memory device, comprising: memory cell array blocks arranged in rows and columns and each containing a plurality of memory sections each having memory cells connected to word lines extending in the row direction and bit lines extending in the column direction, said memory cell array blocks including first and second memory cell array blocks disposed in a first row of memory cell array blocks and third and fourth memory cell array blocks disposed in a second row of memory cell array blocks adjacent to said first row of memory cell array blocks;   select lines extending in the column direction across said respective memory sections of each said memory cell array block;   a first peripheral circuit arranged between (1) the first and second memory cell array blocks in said first row and (2) the third and fourth memory cell array blocks in said second row;   a second peripheral circuit having first and second peripheral circuit portions each including a decoder for selecting said word lines, said first peripheral circuit portion of said second peripheral circuit arranged between said first and second memory cell array blocks and said second peripheral circuit portion of said second peripheral circuit arranged between said third and fourth memory cell array blocks;   a third peripheral circuit having first, second, third, and fourth peripheral circuit portions each including a decoder for selecting said select lines, said first peripheral circuit portion of said third peripheral circuit arranged between the memory sections of said first memory cell array block and said first peripheral circuit, said second peripheral circuit portion of said third peripheral circuit arranged between the memory sections of said second memory cell array block and said first peripheral circuit, said third peripheral circuit portion of said third peripheral circuit arranged between the memory sections of said third memory cell array block and said first peripheral circuit, and said fourth peripheral circuit portion of said third peripheral circuit arranged between the memory sections of said fourth memory cell array block and said first peripheral circuit; and   sense amplifiers arranged between the memory sections of each of said memory cell array blocks..Iaddend..Iadd.60. The semiconductor memory device according to claim 59, further comprising:   a fourth peripheral circuit including circuit elements arranged around a periphery of said memory cell array blocks..Iaddend..Iadd.61. A semiconductor memory device, comprising:   memory cell array blocks arranged in rows and columns and each containing a plurality of memory sections each having memory cells connected to word lines extending in the row direction and bit lines extending in the column direction, said memory cell array blocks including first, second, third, and fourth memory cell array blocks disposed in a first row of memory cell array blocks and fifth, sixth, seventh, and eighth memory cell array blocks disposed in a second row of memory cell array blocks adjacent to said first row of memory cell array blocks;   select lines extending in the column direction across said respective memory sections of each said memory cell array block;   a first peripheral circuit arranged between (1) the first, second, third, and fourth memory cell array blocks in said first row and (2) the fifth, sixth, seventh, and eighth memory cell array blocks in said second row;   a second peripheral circuit having first, second, third, and fourth peripheral circuit portions each including a decoder for selecting said word lines, said first peripheral circuit portion of said second peripheral circuit arranged between said first and second memory cell array blocks, said second peripheral circuit portion of said second peripheral circuit arranged between said third and fourth memory cell array blocks, said third peripheral circuit portion of said second peripheral circuit arranged between said fifth and sixth memory cell array blocks, and said fourth peripheral circuit portion of said second peripheral circuit arranged between said seventh and eighth memory cell array blocks;   a third peripheral circuit having first, second, third, fourth, fifth, sixth, seventh, and eighth peripheral circuit portions each including a decoder for selecting the select lines connected to a corresponding one of said memory cell array blocks, each respective peripheral circuit portion of said third peripheral circuit arranged between the memory sections of the respective corresponding memory cell array block and said first peripheral circuit; and   sense amplifiers arranged between the memory sections of each of said   
     
     
        memory cell array blocks..Iaddend..Iadd.62.  A semiconductor memory device comprising: a memory cell array having four blocks obtained by dividing the memory cell array in the column and row directions, wherein each of said four blocks are further divided in the column direction to form a plurality of sections;   a first peripheral circuit provided between the blocks divided in the column direction of the memory cell array, each of said sections further including a word line extending in the row direction and coupled to said first peripheral circuit;   a second peripheral circuit including first and second peripheral circuit portions which are spaced from each other in a same column, and third and fourth peripheral circuit portions which are spaced from each other in another same column, each of said first, second, third and fourth peripheral circuit portions including a first decoder, each of said first, second, third and fourth peripheral circuit portions being electrically coupled to one of said four blocks, respectively;   a third peripheral circuit provided in the column direction between the first peripheral circuit and the respective adjacent block and including a second decoder; and   sense amplifiers provided between neighboring sections in each of said four blocks..Iaddend..Iadd.63. The semiconductor memory device according to claim 62, wherein each of said four blocks is divided into 2 n  (n: a natural number) sections, each section constituting a minimal memory cell   
     
     
        array unit..Iaddend..Iadd.64.  The semiconductor memory device according to claim 62, wherein said first decoder comprises a row decoder..Iaddend..Iadd.65. The semiconductor memory device according to claim 62, wherein said second decoder comprises a column decoder..Iaddend..Iadd.66. The semiconductor memory device according to claim 62, wherein each said column select line extends across the sections in its respective block..Iaddend..Iadd.67. The semiconductor memory device according to claim 66, wherein each said column select line extends from said third peripheral circuit..Iaddend..Iadd.68. The semiconductor memory device according to claim 67, wherein said first decoder comprises a row decoder and said second decoder comprises a column decoder..Iaddend..Iadd.69. The semiconductor memory device according to claim 68, wherein said first peripheral circuit comprises a bus line extending in the column direction and coupled to said row 
     
     
        decoder..Iaddend..Iadd.70.  The semiconductor memory device according to claim 62, wherein said memory cell array is a dynamic random access memory cell array..Iaddend..Iadd.71. The semiconductor memory device according to claim 62, wherein said memory cell array is a static random access memory cell array..Iaddend..Iadd.72. The semiconductor memory device according to claim 62, further comprising a fourth peripheral circuit provided at an outer margin of the memory cell array, said fourth peripheral circuit comprising bonding pads and input protection circuitry..Iaddend..Iadd.73. The semiconductor memory device according to claim 62, further comprising gating circuits formed between neighboring sections of each of said blocks..Iaddend.