Power and signal line bussing method for memory devices

Abstract

A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.

What is claimed is: 
     
       1. A memory device formed on a semiconductor substrate having .Iadd.peripheral .Iaddend.circuitry positioned adjacent a single memory cell array, said memory device comprising: a plurality of power lines formed above said single memory cell array for supplying power to said .Iadd.peripheral .Iaddend.circuitry, each power line being substantially parallel to and spaced apart from every other power line; and   a plurality of ground lines formed above said single memory cell array for supplying ground potential to said .Iadd.peripheral .Iaddend.circuitry, each ground line being substantially parallel to and spaced apart from every other ground line.   
     
     
       2. A memory device according to claim 1, further comprising at least one signal line formed directly above said single memory cell array to carry signals to said .Iadd.peripheral .Iaddend.circuitry. 
     
     
       3. A method of forming power and signal lines on a memory device, said memory device being formed on a semiconductor substrate and having a single memory cell array .Iadd.and peripheral circuitry adjacent said memory cell array.Iaddend., comprising the steps of: forming a plurality of substantially parallel power lines above said single memory cell array .Iadd.for supplying power to said peripheral circuitry.Iaddend.;   forming a plurality of substantially parallel ground lines above said single memory cell array .Iadd.for supplying ground potential to said peripheral circuitry.Iaddend.; and   forming a plurality of signal lines above said single memory cell array .Iadd.for supplying signals to said peripheral circuitry.Iaddend.. .Iadd.4. A memory device according to claim 1, wherein the plurality of parallel power lines and the plurality of parallel ground lines are positioned in an adjacent alternating pattern. .Iaddend..Iadd.5. A method of forming according to claim 3, wherein said forming steps for the plurality of parallel power lines and the plurality of parallel ground lines result in the power and ground lines being positioned in an adjacent   
     
     
        alternating pattern. .Iaddend..Iadd.6.  A memory device according to claim 1, wherein the plurality of power lines and the plurality of ground lines form a shield layer above the memory cell array and below a package material layer to reduce soft errors. .Iaddend..Iadd.7. A memory device according to claim 2, wherein said at least one or more of the signal lines form a shield layer above the memory cell array and below a package material layer to reduce soft errors. .Iaddend..Iadd.8. A method of forming according to claim 3, further comprising a step of forming a shield layer above the memory cell and below a package material layer to reduce soft errors, said shield layer being composed of said power, ground and signal lines. .Iaddend.