Method of automatically measuring the horizontal scan frequency of a composite synchronism signal, and an electronic circuit operating in accordance with the method

Abstract

A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency. The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.

We claim: 
     
       1. Method of automatically measuring the broadcasting standard of a composite synchronism video signal comprising synchronization impulses at horizontal line frequency, characterized in that it comprises the following steps: effecting a count of a number of impulses, which impulses have a repeat frequency higher than said line frequency, intervening between two successive, line frequency impulses to produce a count value representative of the line frequency;   storing the said count value, corresponding to said number of impulses, to obtain the line frequency; and   effecting successive check counts, .[.int he.]. .Iadd.in the .Iaddend.reverse order, of the same said impulses between subsequent line frequency impulses until a change of frequency of the composite synchronism signal is detected.   
     
     
       2. An electronic circuit for automatically measuring the horizontal synchronization frequency of a composite synchronism signal comprising horizontal synchronization impulses at a line frequency and at least one synchronization impulse at vertical frequency, characterized in that it comprises: a timer receiving on its input said synchronization signal and a clock signal having a predetermined repeat frequency higher than said line frequency;   a counter connected downstream from the timer to detect the number of the impulses at clock frequency between two successive impulses at line frequency, said number of impulses being representative of the line frequency;   a memory connected two-directionally to the counter for storing said number of impulses; and   control logic having inputs connected to outputs of said timer and said counter, and outputs connected to respective inputs of the counter and the memory to enable up or down counting and storing based upon timing signals from the timer.   
     
     
       3. A circuit according to claim 2, characterized in that said control logic comprises a circuit portion for detecting the change of frequency in said composite synchronism signal. 
     
     
       4. A circuit according to claim 2, characterized in that said control logic comprises a circuit portion effective to enable the counter to perform said up or down counting. 
     
     
       5. A circuit according to claim 3, characterized in that said control logic comprises a logic gate of the exclusive OR type having an output connected to said circuit portion and a plurality of inputs connected directly to respective outputs of the counter to check that the down count by said counter has actually gone back to zero. 
     
     
       6. A circuit according to claim 3, characterized in that said circuit portion comprises a shift register and a logic gate connected downstream from said register. 
     
     
       7. A circuit according to claim 2, characterized in that said timer comprises a frequency divider whereto said synchronization signal is input directly and which has an output connected to the input side of a logic gate receiving on another input said clock signal. 
     
     
       8. A circuit according to claim 5, characterized in that said gate of the exclusive OR type carries out a check on a predetermined number of most meaningful bits of the counter. 
     
     
       9. A circuit according to claim 5, characterized in that said gate of the exclusive OR type carries out a check on the n-1 most meaningful bits of the counter. .Iadd. 
     
     
       10.  A method for measuring the horizontal scan frequency of a composite synchronism signal, comprising the steps of: (a) initially measuring the duration between adjacent synchronization pulses, to obtain a stored value therefrom; and thereafter   (b) intermittently comparing the duration between adjacent synchronization pulses to said stored value, to ascertain whether the duration between adjacent synchronization pulses is significantly different from said stored value; and   (c) repeating said step (b) intermittently, until said step (b) indicates, for a predetermined plurality of repetitions, that the duration between adjacent synchronization pulses is significantly different from said stored value, and then initiating a resynchronization process and performing said step (a). .Iaddend..Iadd.11. The method of claim 10, wherein said step (a) of measuring consists of counting clock pulses. .Iaddend..Iadd.12. The method of claim 10, wherein said step (b) of intermittently comparing is performed periodically. .Iaddend..Iadd.13. The method of claim 10, wherein said step (b) of comparing is performed at   
     
     
        regular intervals of a predetermined number of lines. .Iaddend..Iadd.14. The method of claim 10, wherein said step (b) of comparing ignores at least one least-significant bit position. .Iaddend..Iadd.15. A circuit for measuring the horizontal scan frequency of a composite synchronism signal, comprising: input circuitry connected to receive the composite synchronism signal and a clock signal, and to generate therefrom a first output which repeatedly, at intervals determined by a count of said pulses of the composite synchronism signal, provides a burst of clock pulses corresponding to the separation between adjacent pulses in the composite synchronism signal, and   at least a first additional output which repeatedly, at intervals determined by a count of said pulses of the composite synchronism signal, provides a pulse after the end of said burst of clock pulses on said first output;     an up/down counter;   a memory connected to controllably transfer data to and receive data from said counter; and   logic circuitry connected to control transfer of data to and from said memory, and to control an up/down input of said counter, and to detect when said counter has a count value of approximately zero;   said logic circuitry being configured to initially operate said counter in a first up/down direction to count pulses in one of said bursts, and thereafter   to transfer an initial count value from said counter into said memory, and thereafter,   on each occurrence of a pulse on said first additional output, to cause said counter to operate in a second up/down direction starting from said initial count value, and then to detect whether said counter reaches a count value of approximately zero;   said logic circuitry returning said counter to operation in said first up/down direction whenever said logic circuitry twice successively detects that said counter, while operating in a second up/down direction starting from said initial count value, has not reached a count value of approximately zero. .Iaddend..Iadd.16. The circuit of claim 15, wherein said input circuitry is a timer. .Iaddend..Iadd.17. The circuit of claim 15, wherein said logic circuitry, in detecting said counter has a count value of approximately zero, ignores at least one least-significant bit of the count value. .Iaddend..Iadd.18. The circuit of claim 15, wherein said input circuitry timer further comprises a second additional output which repeatedly, at intervals determined by a count of said pulses of the composite synchronism signal, provides a pulse after the end of said burst of clock pulses on said first output and prior to said pulse on said first additional output. .Iaddend.