Synchronous semiconductor memory device having an auto-precharge function

Abstract

A semiconductor memory device according to the present invention having a plurality of memory banks, a row address strobe signal buffer, a column address strobe signal buffer and a column address generator and performing a data access operation in response to the burst length and latency information related to a system clock having a predetermined frequency, comprises a device for generating a signal which automatically precharges one memory bank of the memory banks in response to the row address strobe signal and the signal having the burst length and latency information after an address operation for the memory bank is completed.

What is claimed is: 
     
       1. A semiconductor memory device using row and column address strobe signals comprising: a plurality of memory banks each including a plurality of memory cells; and   means for generating a signal which automatically precharges at least one memory bank of said memory banks in response to receiving a signal which corresponds to said row and column address strobe signals after an address operation for said memory bank is completed, said address operation activating at least one of said plurality of memory cells.   
     
     
       2. A semiconductor memory device which performs a data access operation in response to burst length and latency information related to a system clock having a predetermined frequency, said semiconductor memory device comprising: a plurality of memory banks;   a row address strobe signal buffer;   a column address strobe signal buffer;   a column address generator; and   means for generating a signal which automatically precharges one memory bank of said memory banks in response to said column address strobe signal and said burst length and latency information after an address operation for said memory bank is completed.   
     
     
       3. A semiconductor memory device which performs a data access operation in response to burst length and latency information related to a system clock having a predetermined frequency, said semiconductor memory device comprising: a plurality of memory banks each including a plurality of memory cells;   a circuit generating a row master clock for driving row related control circuits which are included in one memory bank of said memory banks in response to a row address strobe signal applied externally and a bank selection signal; and   a circuit which generates said row master clock, said circuit being supplied with a signal generated in response to said row address strobe signal and said burst length and latency information after an address operation for one memory bank of said memory banks is completed, said address operation activating at least one of said plurality of memory cells.   
     
     
       4. A semiconductor memory device which performs a data access operation in response to burst length and latency information related to a system clock having a predetermined frequency, said semiconductor memory device comprising: a plurality of memory banks including a plurality of memory cells;   a row master clock generating circuit which generates a row master clock for driving row related control circuits that are included in one memory bank of said memory banks in response to a row address strobe signal applied externally and a bank selection signal;   a column master clock generating circuit which receives a column address strobe signal externally and then generates a column master clock for driving column related control circuits which are included in said one memory bank of said memory banks,   a column address generating circuit which receives address signals externally and then generates column address signals; and   a circuit which generates said row master clock, said circuit being supplied with a signal generated in response to said row address strobe signal and said burst length and latency information after an address operation for one memory bank of said memory banks is completed, said address operation activating at least one of said plurality of memory cells.   
     
     
       5. A semiconductor memory device having a plurality of memory banks including a plurality of memory cells, and a circuit generating a row master clock for driving row related control circuits which are included in one memory bank of said memory banks in response to a row address strobe signal applied externally and a bank selection signal, a circuit receiving a column.[.a.]. address strobe signal externally and then generating a column master clock for driving column related control circuits which are included in one memory bank of said memory banks, and a circuit receiving address signals externally and then generating column address signals and performing a data access operation in response to burst length and latency information related to a system clock having a predetermined frequency, said semiconductor memory device comprising: means for generating a timing control signal corresponding to said row master clock;   a circuit which receives said timing control signal and said burst length and latency information and then generates said column address strobe signal and an information detection signal derived from said burst length and latency information; and   means for transferring to a circuit which generates said row master clock a precharge signal responding to a signal which contains said burst length, a column address signal and said information detection signal. .Iadd.   
     
     
       6.  A method of operating a semiconductor memory device responsive to row and column address strobe signals, comprising the steps of: addressing at least one memory cell in a bank of memory cells; and   generating a signal which automatically precharges the bank of memory cells in response to receiving a signal which corresponds to the row and column address strobe signals after said addressing step is completed..Iaddend..Iadd.7. A method of operating a semiconductor memory device, comprising the steps of:   generating a column address strobe signal;   addressing at least one memory cell in a bank of memory cells; and   generating a signal which automatically precharges the bank of memory cells in response to the column address strobe signal and burst length and latency information which is related to a system clock having a predetermined frequency, after said addressing step has been completed..Iaddend..Iadd.8. A method of operating a semiconductor memory device, comprising the steps of:   addressing at least one memory cell in a bank of memory cells;   generating a row master clock signal from row related control circuits electrically coupled to the bank of memory cells, in response to a row address strobe signal and a bank selection signal; and   generating a signal to precharge the bank of memory cells, in response to the row address strobe signal and burst length and latency information which is related to a system clock having a predetermined frequency, after   
     
     
        said addressing step has been completed..Iaddend..Iadd.9.  The method of claim 8, further comprising the steps of: generating a column master clock signal in response to a column address strobe signal; and   generating a column address which contains bank selection information and autoprecharge information, in response to an address..Iaddend..Iadd.10. The method of claim 8, further comprising the steps of:   generating a timing control signal in response to the row master clock signal;   generating a burst/latency information detection signal in response to the timing control signal..Iaddend..Iadd.11. The method of claim 10, wherein a timing of said step of generating a burst/latency information detection signal varies depending on a value of the burst length and a value of the latency information; and wherein said step of generating a signal to precharge the bank of memory cells is performed in response to the burst/latency information detection signal..Iaddend..Iadd.12. A method of operating a synchronous DRAM memory device during a burst reading mode, comprising the steps of:   activating a row master clock signal during a first time interval;   generating a column address in response to a column address strobe signal;   reading data from the memory device during the first time interval, in response to the column address strobe signal;   generating a precharge signal during the first time interval, in response to the column address;   deactivating the row master clock signal in response to the precharge signal; and   precharging the memory device during a second time interval following the first time interval, in response to the precharge   
     
     
        signal..Iaddend..Iadd.     The method of claim 12, further comprising the steps of: activating a column master clock signal during the first time interval, in response to the column address strobe signal; and   generating a burst length detection signal during the first time interval, in response to the column address and the column master clock signal; and   wherein said step of generating a precharge signal comprises generating a precharge signal during the first time interval, in response to the column address and the burst length detection signal..Iaddend..Iadd.14. The method of claim 13, further comprising the steps of:   generating a column address activating detection signal, in response to the column address and the burst length detection signal; and   generating a timing control signal, in-sync with said step of activating a row master clock signal..Iaddend..Iadd.15. The method of claim 14, further comprising the steps of:   generating a burst/latency information signal, in response to the burst length detection signal; and   generating a burst latency information detection signal, in response to the burst/latency information signal, the timing control signal and the column address activating detection signal..Iaddend..Iadd.16. The method of claim 15, wherein said step of generating a precharge signal comprises generating a precharge signal during the first time interval, in response to the column address, the burst length detection signal and the burst   
     
     
        latency information detection signal..Iaddend..Iadd.17.  The method of claim 12, wherein said step of generating a precharge signal overlaps in time with said step of reading data from the memory device..Iaddend..Iadd.18. A method of operating a synchronous DRAM memory device during a burst mode having a burst length and a column address strobe latency, comprising the steps of: activating a row master clock signal during a first time interval;   activating a word line electrically coupled to a row of memory cells in the memory device in response to the row master clock signal;   generating a column address in response to a column address strobe signal;   generating a burst length signal;   generating, in response to the column address, a precharge signal at a first point in the first time interval if the burst length does not correspond to the burst length signal and at a second point in the first time interval if the burst length corresponds to the burst length signal;   deactivating the row master clock signal in response to the precharge signal; and   precharging the memory device in response to the precharge signal..Iaddend..Iadd.19. The method of claim 18, wherein said step of precharging the memory device includes the step of deactivating the word line..Iaddend..Iadd.20. The method of claim 18, wherein the second point in the first time interval is delayed in time relative to the first point   
     
     
        in the first time interval..Iaddend..Iadd.21.  The method of claim 18, further comprising the step of generating a latency signal; and wherein said step of generating a precharge signal comprises generating, in response to the column address, a precharge signal at the first point in the first time interval if the burst length corresponds to the burst length signal and the latency signal corresponds to the column address strobe latency..Iaddend..Iadd.22. The method of claim 21, wherein said step of generating a precharge signal comprises generating, in response to the column address, a precharge signal at the second point in the first time interval if the burst length does not correspond to the burst length signal or if the column address strobe latency does not correspond to the latency signal..Iaddend..Iadd.23. The method of claim 22, wherein the second point in the first time interval is delayed in time relative to the first point in the first time interval..Iaddend..Iadd.24. A method of operating a synchronous DRAM memory device during a burst mode, comprising the steps of: activating a row master clock signal during a first time interval;   activating a word line electrically coupled to a row of memory cells in the memory device in response to the row master clock signal;   writing data to the memory device during a write time interval;   reading data from the memory device during a read time interval;   generating a column address in response to a column address strobe signal;   generating, in response to the column address, a precharge signal at a first point in the first time interval if the read time interval overlaps the first time interval and at a second point in the first time interval if the write time interval overlaps the first time interval;   deactivating the row master clock signal in response to the precharge signal; and   precharging the memory device in response to the precharge   
     
     
        signal..Iaddend..Iadd.25.  The method of claim 24, wherein said step of precharging the memory device comprises the step of deactivating the word line..Iaddend..Iadd.26. The method of claim 24, wherein the second point in the first time interval is delayed in time relative to the first point in the first time interval..Iaddend..Iadd.27. A synchronous DRAM memory device, comprising: a row address strobe buffer which activates a row master clock signal during a first time interval in response to a row address strobe signal and deactivates the row master clock signal at an end of the first time interval in response to a precharge signal;   a memory bank, responsive to the row master clock signal; and   a precharge signal generator which generates the precharge signal during the first time interval, in response to a column address..Iaddend..Iadd.28. The memory device of claim 27, wherein said precharge signal generator generates the precharge signal in response to the column address and a burst length detection signal..Iaddend..Iadd.29. The memory device of claim 27, further comprising an end-of-burst detector which generates a burst length detection signal in response to a column master clock signal; and wherein said precharge signal generator generates the precharge signal in response to the column address and a burst length   
     
     
        detection signal..Iaddend..Iadd.30.  The memory device of claim 29, further comprising: a burst/latency information signal generator which generates a burst/latency information signal in response to burst length detection signal and at least one of a latency signal, a write enable activating information signal and a burst length signal; and   a timing control circuit which generates a timing control signal in response to the row master clock signal..Iaddend..Iadd.31. The memory device of claim 30, further comprising a burst/latency information detector which generates a burst latency information detection signal in response to the timing control signal and the burst/latency information signal; and wherein said precharge signal generator generates the precharge signal in response to the column address, the burst length detection signal and the burst latency information detection signal..Iaddend..Iadd.32. The memory device of claim 31, wherein said precharge signal generator generates a column address activating detection signal; and wherein said burst/latency information detector generates a burst latency information detection signal in response to the timing control signal, the burst/latency information signal and the column   
     
     
        address activating detection signal..Iaddend..Iadd.33.  A synchronous memory device, comprising: an address generator which generates a first control signal in response to an auto-precharge command signal;   a burst detector which generates an end of burst signal by detecting a timing of an end of a burst operation; and   an auto-precharge signal generator which generates an auto-precharge signal to automatically precharge at least one memory bank of a plurality of memory banks in response to the end of burst signal and the first control signal..Iaddend..Iadd.34. A synchronous memory device, comprising:   an address generator which generates a first control signal in response to an auto-precharge command signal which is provided in sync with an external clock signal;   a burst detector which generates an end of burst signal by detecting a timing of an end of a burst operation;   an auto-precharge signal generator which generates an auto-precharge signal to automatically precharge at least one memory bank of a plurality of memory banks in response to the end of burst signal and the first control signal; and   a row addressing circuit which designates a row in a memory array in accordance with a given row address combination, and designates a precharging row in response to the auto-precharge   
     
     
        signal..Iaddend..Iadd.     A semiconductor memory device which performs a burst operation according to a predetermined latency information signal and a burst length information signal which are provided in-sync with an external clock signal, comprising: a plurality of memory banks;   a burst detector which generates an end of burst signal by detecting a timing of an end of the burst operation; and   an auto-precharge signal generator which generates an auto-precharge signal to automatically precharge at least one of said plurality of memory banks in response to the end of burst signal and the latency information signal and the burst length information signal..Iaddend..Iadd.36. A semiconductor memory device which performs a burst operation according to a predetermined latency and burst length information set by a user, in-sync with an external clock signal, said semiconductor memory device comprising:   a plurality of memory banks;   a burst detector which generates an end of burst signal by detecting a timing of the end of said burst operation;   an auto-precharge signal generator which generates an auto-precharge signal to automatically precharge at least one memory bank of said plurality of memory banks in response to the end of burst signal and the predetermined latency and the burst length information, and wherein said auto-precharge signal is enabled when the burst operation is completed; and   a row addressing circuit which designates a row in the at least one memory bank in accordance with a given row address combination, and designates a precharging row in response to the auto-precharge   
     
     
        signal..Iaddend..Iadd.     The semiconductor memory device of claim 36, wherein the row addressing circuit designates a row in said plurality of memory banks in accordance with a given row address combination and precharges a row in at least one of said plurality of memory banks in response to the auto-precharge signal and a bank selection signal..Iaddend.