Sense circuit for reading data stored in nonvolatile memory cells

Abstract

A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC max . The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

What we claim is: 
     
       1. A sense circuit for reading EPROM and/or ROM type memory cells, programmable in an ON-condition or in an OFF-condition, organized in an array of columns and rows of cells, selectively addressable through row lines and bit lines, employing a differential amplifier for discriminating the conductivity of a selected array cell from the conductivity of a reference cell in an ON-condition, functionally connected in series to a first branch and to a second branch, respectively, of an input circuit of said differential amplifier, between a supply rail and ground, and offsetting means, capable of causing a discriminating unbalancing between the values of the currents flowing through said two branches of the input circuit of the differential amplifier, between the supply rail and ground, characterized by the fact that said offsetting means is an offsetting current generating circuit formed by   at least a .Iadd.first .Iaddend.transistor (n1) having electrical characteristics equivalent to the electrical characteristics of anyone cell of said memory cells programmed in an ON-condition, and having a gate to which a driving voltage essentially identical to the voltage applied to a gate of a selected array cell to be read is applied for generating a first current (I on ) substantially identical to the current flowing through a selected array cell which is programmed in an .[.ONcondition.]. .Iadd.ON condition.Iaddend.;   a first current mirror capable of mirroring said first generated current (I on ) in an output branch of said first mirror;   a second current mirror, connected to said output branch of said first current mirror and capable of splitting said first current (I on ) into two identical semicurrents, one of which (.[. offset  .]. .Iadd.I offset  .Iaddend.) is forced through said first branch of said input circuit of said differential amplifier comprising said selected array cell to be read thus causing said discriminating current unbalance;   said driving voltage of said first transistor being provided by means of a supplementary row of cells, which supplementary row is decoded at every reading and which replicates, during transients, the electrical behaviour of the row of the array which includes said selected cell to be read.   
     
     
       2. A sense circuit for reading EPROM and/or ROM type memory cells, programmable in an ON-condition or in an OFF-condition, organized in an array of columns and rows of cells, selectively addressable through row lines and bit lines, employing a differential amplifier for discriminating the conductivity of a selected array cell from the conductivity of a reference cell in an ON-condition, functionally connected in series to a first branch and to a second branch, respectively, of an input circuit of said differential amplifier, between a supply rail and ground, and offsetting means capable of causing a discriminating unbalancing between the values of the currents flowing through said two branches of the input circuit of the differential amplifier, between the supply rail and ground, characterized by the fact that said offsetting means is an offsetting current generating circuit formed by at least a .Iadd.first .Iaddend.transistor (n1) having electrical characteristics equivalent to the electrical characteristics of anyone cell of said memory cells programmed in an ON-condition, and having a gate to which a driving voltage essentially identical to the voltage applied to a gate of a selected array cell to be read is applied for generating a first current (I on ) substantially identical to the current flowing through a selected array cell which is programmed in an .[.ONcondition.]. .Iadd.ON condition.Iaddend.;   a second transistor (n2) having electrical characteristics equivalent to the electrical characteristics of anyone of said memory cells programmed in an OFF-condition, connected substantially in parallel with said first transistor (n1) for generating an additional current (I off ) which is substantially identical to the current flowing through a selected array cell programmed in an OFF-condition;   a first current mirror capable of mirroring a sum current (I on  +I off ) of said currents generated by said first and said second transistors in an output branch of said first mirror;   a second current mirror, connected to said output branch of said first mirror and capable of splitting said sum current into two identical semicurrents, one of which (I offset ) is forced through said first branch of said input circuit of said differential amplifier which includes said selected array cell to be read, thus determining said discriminating current unbalance;   a third transistor (n6), having the same characteristics of said second transistor (n2), connected into said second branch of said input circuit including said reference cell and having a gate to which a driving voltage essentially identical to the voltage which is applied to the gate of said selected cell to be read is applied for forcing a current identical to said additional current (I off ) through said second branch of said input circuit including said reference cell;   said driving voltage of said first, second and third transistors, being provided by a supplementary row of cells which is decoded at every reading and which replicates, during transients, the electrical behaviour of the row of the array which contains said selected cell to be read;   the reading conditions of a memory cell programmed in an ON-condition and of a memory cell programmed in an OFFcondition being represented, respectively, by the disequalities between the currents which flow through said second branch containing said reference cell (I ref ) and said first branch containing said cell to be read (I mat ): I ref  <I mat  and I ref  >I mat , respectively, and which are detected by means of said differential amplifier, being satisfied both by the univocal condition: I on  >I off , which is intrinsically true.   
     
     
       3. A sense circuit for reading EPROM and/or ROM type memory cells, programmable in an ON-condition or in an OFF-condition, organized in an array of columns and rows of cells, selectively addressable through row lines and bit lines, employing a differential amplifier for discriminating the conductivity of selected array cell from the conductivity of a reference cell in an ON-condition, functionally connected in series to a first branch and to a second branch, respectively, of an input circuit of said differential amplifier, between a supply rail and ground, and offsetting means capable of causing a discriminating unbalancing between the values of the currents flowing through said two branches of the input circuit of the differential amplifier, between the supply rail and ground, characterized by the fact that said offsetting means is an offsetting current generating circuit formed by   at least a .Iadd.first .Iaddend.transistor (n1) having electrical characteristics equivalent to the electrical characteristics of anyone cell of said memory cells programmed in an ON-condition, and having a gate to which a driving voltage essentially identical to the voltage applied to a gate of a selected array cell to be read is applied for generating a first current (I on ) substantially identical to the current flowing through a selected array cell which is programmed in an ON-condition;   a first current mirror capable of mirroring said first generated current (I on ) in an output branch of said first mirror;   a second current mirror, connected to said output branch of said first current mirror and capable of splitting said first current (I on ) into two identical semicurrents, one of which (I offset ) is forced through said first branch of said input circuit of said differential amplifier comprising said selected array cell to be read thus causing said discriminating current unbalance;   a second transistor (n6'), having electric characteristics equivalent to the characteristics of anyone cell of said memory cells programmed in an OFF-condition, connected into said second branch of said input circuit which contains said reference cell and having a gate to which a driving voltage of a fractionary value in respect to the voltage of said supply rail, is applied for forcing a current (.[.I off  .]. .Iadd.I' offset  .Iaddend.) of fractionary value in respect to the current which flows through a selected array memory cell programmed in an OFF-condition.[., condition,.]. through said second branch of said input circuit which contains said reference cell;   said driving voltage of said first transistor being essentially identical to the voltage applied to the gate of the selected array cell to be read and being provided by a supplementary row of cells, which is decoded at every reading and which replicates during transients, the electrical behaviour of the row of the array which contains said selected cell to be read. .Iadd.   
     
     
       4.  A read circuit for determining the state of a matrix nonvolatile memory cell, which, in response to a read signal, generates a read current equal to an on current if programmed in an on state and equal to an off current that is less than said on current if programmed in an off state comprising: a matrix line coupled to said memory cell and operable to conduct a unidirectional matrix current that equals the sum of said read current and an offset current;   a reference line operable to conduct a reference current that is greater than said offset current;   a reference circuit coupled to said reference line and operable to generate said reference current in response to said read signal;   an offset circuit coupled to said matrix line and operable to generate said offset current in response to said read signal; and   a differential amplifier coupled between said matrix and reference lines and operable to compare said matrix current with said reference current. .Iaddend..Iadd.5. The read circuit of claim 4 wherein said reference   
     
     
        current is substantially equal to said on current. .Iaddend..Iadd.6.  The read circuit of claim 4 wherein said reference current substantially equals the sum of said on and off currents. .Iaddend..Iadd.7. The read circuit of claim 4 wherein said reference current substantially equals the sum of said on current and a fraction of said off current. .Iaddend..Iadd.8. The read circuit of claim 4 wherein said offset current equals a fraction of said on current. .Iaddend..Iadd.9. The read circuit of claim 4 wherein said offset current substantially equals one half of said on current. .Iaddend..Iadd.10. The read circuit of claim 4 wherein said offset current equals a fraction of the sum of said on and off 
     
     
        currents. .Iaddend..Iadd.11.  The read circuit of claim 4 wherein said offset current substantially equals one half of the sum of said on and off currents. .Iaddend..Iadd.12. The read circuit of claim 4 wherein said offset circuit comprises a dummy row of nonvolatile memory cells that are operatively coupled to receive said read signal. .Iaddend..Iadd.13. A method for reading a nonvolatile memory cell, comprising: generating in response to a read signal a matrix current that equals the combination of a read current and an offset current;   generating in response to said read signal a reference current, which, during a transient period following activation of said nonvolatile memory cell, is less than or equal to said matrix current when said cell is in an on state, and which is greater than or equal to said matrix current when said cell is in an off state; and   comparing said matrix current to said reference current. .Iaddend..Iadd.14. The method of claim 13 wherein said reference current is substantially   
     
     
        equal to the on current of said memory cell. .Iaddend..Iadd.15.  The method of claim 13 wherein said reference current is substantially equal to the sum of the on and off currents of said memory cell. .Iaddend..Iadd.16. The method of claim 13 wherein said reference current is substantially equal to the sum of the on current and a fraction of the off current of said memory cell. .Iaddend..Iadd.17. The method of claim 13 wherein said offset current is equal to a fraction of the on current of said memory cell. .Iaddend..Iadd.18. The method of claim 13 wherein said offset current is substantially equal to one half of the on current of said memory cell. .Iaddend..Iadd.19. The method of claim 13 wherein said offset current is equal to a fraction of the sum of the on and off currents of said memory cell. .Iaddend..Iadd.20. The method of claim 13 wherein said offset current is substantially equal to one half of the sum of the on and off currents of said memory cell. .Iaddend..Iadd.21. The method of claim 13 wherein said generating a matrix current comprises coupling said read signal to a row of nonvolatile memory cells that are similar to said memory cell to generate said offset current. 
     
     
        .Iaddend..Iadd.22.  A circuit for reading a matrix nonvolatile memory cell having an input coupled to a word line, which is coupled to an address decoder, and having an output, comprising: an offset drive line that is at substantially a same potential as said word line during a transient period of a read of said cell;   a reference drive line;   a matrix line coupled to said memory-cell output;   a reference line;   a differential amplifier having a first input coupled to said matrix line and a second input coupled to said reference line;   a reference-current generator having an input coupled to said reference drive line and an output coupled to said reference line; and   an offset-current generator having an input coupled to said offset drive   
     
     
        line and an output coupled to said matrix line. .Iaddend..Iadd.23.  The circuit of claim 22 wherein said reference drive line is at substantially 
     
     
        said same potential during said read of said cell. .Iaddend..Iadd.24.  The circuit of claim 22 wherein said reference-current generator comprises a first reference nonvolatile memory cell programmed in an on state and having an input and an output respectively coupled to said reference-current generator input and output. .Iaddend..Iadd.25. The circuit of claim 24 wherein said reference-current generator further comprises a second reference nonvolatile memory cell programmed in an off state and having an output coupled to said output of said reference-current generator. .Iaddend..Iadd.26. The circuit of claim 25 wherein said second reference nonvolatile memory cell comprises an input coupled to said input of said reference-current generator. .Iaddend..Iadd.27. The circuit of claim 25 wherein said second reference nonvolatile memory cell comprises an input coupled to said offset drive line. .Iaddend..Iadd.28. The circuit of claim 25 wherein said second reference nonvolatile memory cell comprises an input that is coupled to said offset-current generator. .Iaddend..Iadd.29. The circuit of claim 22 wherein said offset-current generator comprises a dummy row of nonvolatile memory cells each having an input coupled to said offset drive line. .Iaddend..Iadd.30. The circuit of claim 22 wherein said offset-current generator comprises: an input current generator having an input coupled to said input of said offset-current generator and having an output;   a current mirror having an input coupled to said output of said input-current generator and having an output; and   a current divider having an input coupled to said output of said current mirror and an output coupled to said output of said offset-current generator. .Iaddend..Iadd.31. The circuit of claim 30 wherein said input current generator comprises a first nonvolatile memory cell programmed in an on state and having an input and an output respectively coupled to said   
     
     
        input and output of said input current generator. .Iaddend..Iadd.32.  The circuit of claim 31 wherein said input current generator further comprises a second nonvolatile memory cell programmed in an off state and having an input and an output respectively coupled to said input and output of said input current generator. .Iaddend..Iadd.33. The circuit of claim 30 wherein said current divider comprises: first and second diode-connected nonvolatile memory cells programmed in an on state and coupled in parallel to said input of said current divider; and   a third nonvolatile memory cell having an input and output respectively coupled to said input and output of said current divider. .Iaddend..Iadd.34. The circuit of claim 30 wherein said reference-current generator further comprises a reference nonvolatile memory cell programmed in an off state and having an input coupled to said output of said current mirror and having an output coupled to said reference line. .Iaddend.