Semiconductor memory device and method for reading and writing data therein

Abstract

An NAND gate for outputting an output establishment detection signal in response to the fact that a complementary output of a latch type sense amplifier has been established is provided. When a tristate buffer is activated by signal, a word line which has been in a selected state is rendered non-selected state. Accordingly, current can be prevented from leaking from a power supply line to a ground line in tristate buffer. In addition, column current Ic flowing through memory cells can be minimized in response to the fact that word line has been set to a selected state.

What is claimed is: 
     
       1. A semiconductor memory device in which electrical rewriting of data is possible, comprising: a plurality of memory cells arranged in row and column directions;   a word line provided corresponding to each row of memory cells;   a complementary bit line pair provided corresponding to each column of memory cells;   a sense amplifier including a complementary input node pair for amplifying potential difference between the input node pair;   a transfer gate provided between said bit line pair and said input node pair of said sense amplifier;   sensing means for sensing that a complementary output of said sense amplifier has been established; and   a tristate buffer controlled by an output of said sensing means for outputting an output of said sense amplifier to a data bus.   
     
     
       2. The semiconductor memory device according to claim 1, wherein said sense amplifier is a latch type sense amplifier including   first and second transistors of a first conductivity type having their first and second electrodes connected between one of said input node pair and a fast referee potential line and between another of said input node pair and said first reference potential line, and their input electrodes connected to said another input node and said one input node, respectively, and   first and second transistors of a second conductivity type having their fast and second electrodes connected between one of said input node pair and a second reference potential line and between another of said input node pair and said second reference potential line and their input electrodes connected to said another input node and said one input node, respectively.   
     
     
       3. The semiconductor memory device according to claim 1, wherein said sensing means is an AND circuit which receives a complementary output of said sense amplifier.   
     
     
       4. The semiconductor memory device according to claim 1, comprising: read control means for activating a desired memory cell by setting said word line to a selected stat writing potential difference corresponding to data of the memory cell to said input node pair of said sense amplifier, then, cutting off said transfer gate, activating said sense amplifier, and deactivating said memory cell by setting said word line to a non-selected state in response to an output of said sensing means.   
     
     
       5. A method of reading data of a memory cell in a semiconductor memory device including a plurality of memory cells arranged in row and column directions,   a word line provided corresponding to each row of memory cells,   a complementary bit line pair provided corresponding to each column of memory cells,   a sense amplifier having a complementary input node pair for amplifying potential difference between the input node pair,   a transfer gate provided between said bit line pair and said Input node pair of said sense amplifier,   sensing means for sensing that a complementary output of said sense amplifier has been established, and   a tristate buffer controlled by an output of said sensing means for outputting an output of said sense amplifier to a data bus, comprising the steps of:   activating a desired memory cell by setting said word line to a selected state, writing potential difference corresponding to data of the memory cell to the input node pair of said sense amplifier, then, cutting off said transfer gate, activating said sense amplifier, and deactivating said memory cell by setting said word line to a non-selected state in response to an output of said sensing means.   
     
     
       6. A method of continuously reading data of a desired row of memory cells in a semiconductor memory device having a plurality of memory cells for storing data arranged in row and column directions,   a word line provided corresponding to each row of memory cells,   a complementary bit line pair provided corresponding to each column of memory cells.   a selectively activated bit line load provided corresponding to each complementary bit line pair, each bit line load being connected between a bit line pair and a power supply terminal of the semiconductor memory,   read mean for reading data of a desired memory cell, and   a column select gate provided corresponding to each bit line pair, for connecting a bit line pair to which a desired memory cell is connected and said read means to each other, said method comprising the steps of:   applying a signal to each bit line load for causing each complementary bit line pair to be in a floating state;   applying a signal having a prescribed period to a word line corresponding to the desired row, and during said prescribed period, storing the data of each memory cell of said desired row in a floating bit line pair to which each memory cell is connected wherein said data is stored simultaneously in each bit line pair; and thereafter,   sequentially applying a signal to each column select gate for successively connecting and disconnecting each bit line pair, one by one, to and from said read means, wherein potential differences stored in the bit line pairs are continuously transferred to and amplified by said read means;   whereby the word line is rendered conductive only once and data is read continuously, so that a burst read operation is implemented.   
     
     
       7. A method of simultaneously writing data to a desired row of memory cells in a semiconductor memory device having a plurality of memory cells for storing data arranged in row and column directions,   a word line provided corresponding to each row of memory cells,   a complementary bit line pair provided corresponding to each column of memory cells,   a switched bit line load provided corresponding to each complementary bit line pair, each load being connected between a bit line pair and a power supply terminal of the semiconductor memory,   write means for writing data to a desired memory cell, and   a column select gate provided corresponding to each bit line pair, for connecting a bit line pair to which a desired memory cell is connected and said write means is to each other, said method comprising the steps of:   applying a signal to each bit line load for causing each complementary bit line pair to be in a floating state;   sequentially applying a signal to each column select gate for successively connecting and disconnecting, one by one, each floating bit line pair to and from the write means, wherein write data is continuously transferred from said write means to each floating bit line pair; and thereafter,   applying a signal having a prescribed period to a word line corresponding to the desired row, and during said prescribed period, writing the data of each bit line pair to each memory cell of said desired row, wherein said data is written simultaneously into each desired memory cell;   whereby data is written to said bit line pairs continuously, and the word line is rendered conductive only once, so that a burst write operation is implemented. .Iadd.   
     
     
       8.  A semiconductor memory device in which electrical rewriting of data is possible, comprising: a plurality of memory cells arranged in row and column directions;   a word line provided corresponding to each row of memory cells;   a complementary bit line pair provided corresponding to each column of memory cells;   a sense amplifier including a complementary input node pair for amplifying potential difference between the input node pair, said input node pair receiving potentials of a corresponding complementary bit line pair;   sensing means for sensing that a complementary output of said sense amplifier has been established; and   a tristate buffer controlled by an output of said sensing means for outputting an output of said sense amplifier to a data bus. .Iaddend..Iadd.9. The semiconductor memory device according to claim 8, wherein   said sense amplifier is a latch type sense amplifier including   first and second transistors of a first conductivity type having their first and second electrodes connected between one of said input node pair and a first reference potential line and between another of said input node pair and said first reference potential line, and their input electrodes connected to said another input node and said one input node, respectively, and   first and second transistors of a second conductivity type having their first and second electrodes connected between one of said input node pair and a second reference potential line and between another of said input node pair and said second reference potential line, and their input electrodes connected to said another input node and said one input node, respectively. .Iaddend..Iadd.10. The semiconductor memory device according to claim 8, wherein   said sensing means is an AND circuit which receives a complementary output of said sense amplifier. .Iaddend..Iadd.11. The semiconductor memory device according to claim 8, comprising:   read control means for activating a desired memory cell by setting said word line to a selected state, writing potential difference corresponding to data of the memory cell to said input node pair of said sense amplifier, then, activating said sense amplifier, and deactivating said memory cell by setting said word line to a non-selected state in response to an output of said sensing means. .Iaddend..Iadd.12. A method of reading data of a memory cell in a semiconductor memory device including   a plurality of memory cells arranged in row and column directions,   a word line provided corresponding to each row of memory cells,   a complementary bit line pair provided corresponding to each column of memory cells,   a sense amplifier having a complementary input node pair for amplifying potential difference between the input node pair, said input node pair receiving potentials of a corresponding complementary bit line pair,   sensing means for sensing that a complementary output of said sense amplifier has been established, and   a tristate buffer controlled by an output of said sensing means for outputting an output of said sense amplifier to a data bus, comprising the steps of:   activating a desired memory cell by setting said word line to a selected state, writing potential difference corresponding to data of the memory cell to the input node pair of said sense amplifier, then, activating said sense amplifier, and deactivating said memory cell by setting said word line to a non-selected state in response to an output of said sensing means. .Iaddend.