Video signal digital slicing circuit

Abstract

An extractor for digital data transmitted at a first determined frequency (f0) through a video channel after a burst of 0s and 1s emitted at a first frequency (f0). A comparator (1) compares the input signal with a threshold level. A threshold level is provided by an up/down counter (12) operating at a frequency (F0) multiple of the first frequency, the up/down counting input of which is connected to the output of the comparator (1), and a digital/analog converter (16) receiving the output of the up/down counter and supplying the threshold level (V T ).

I claim: 
     
       1. An extractor for digital data transmitted at a first determined frequency (fo) through a video channel after an input signal including a burst of Os and 1s is emitted at said first frequency (fo) onto a first input (VIN) of a comparator (1) for comparing said input signal with a threshold level, the extractor including means for supplying a second frequency (F0) as a multiple by N of the first frequency (fo), and means for supplying said threshold level, operating during said burst .[.duration.]., wherein the means for supplying the threshold level comprises: an up/down counter (12) operating at said multiple frequency (F0), the counter including an up/down counting input connected to an output of said comparator (1), and   a digital/analog converter (16) receiving an output of the up/down counter and supplying said threshold level (VT); and   wherein the comparator output is connected to an edge detector (24) acting, during said burst, on a divider by N (20) of the second frequency (F0) for supplying to a flip-flop (2), connected to the comparator output, a clock signal at the first frequency (fo) with a desired phase relationship.   
     
     
       2. A digital data extractor according to claim 1, wherein the digital/analog converter (16) is of an exponential type. 
     
     
       3. A digital data extractor according to claim 1, wherein the comparator output is connected to a digital filter of a majority detection type (6, 8). 
     
     
       4. A digital data extractor according to claim 1, further including phasing means for establishing during said burst a predetermined phase for said clock signal relative to the output of said comparator, said phasing means comprising said edge detector, said flip-flop and said divider by N, said clock signal derived by said divider by N from said second frequency, said flip-flop sampling the output of said comparator at said first determined frequency (fo) and at said predetermined phase. 
     
     
       5. An extractor for digital data transmitted at a first predetermined frequency (fo) through a video channel after an input signal including a burst of 0s and 1s is emitted at said first frequency (fo), including: a comparator (1) for comparing said input signal with a threshold level, said comparator having a first input (VIN) receiving the digital data and the burst of 0s and 1s;   means for supplying a second frequency (F0) as a multiple by N of the first frequency (fo), and means for supplying said threshold level, operating during said burst .[.duration.].;   said means for supplying the threshold level comprising: an up/down counter (12) operating at said multiple frequency (F0), the counter including an up/down counting input connected to an output of said comparator (1); and   a digital/analog converter (16) receiving an output of the up/down counter and supplying said threshold level (VT); and     further including phasing means for establishing a predetermined phase for a sampling signal derived from said second frequency, said phasing means comprising: an edge detector (24) connected to receive the output of said comparator;   a divider by N (20) operating on the second frequency (F0), said divider by N responsive to an output of said edge detector;   means for providing the output of said edge detector to said divider by N only during said burst; and   a flip-flop (2) connected for sampling the comparator output, said flip-flop receiving from said divider by N a sampling signal having said predetermined phase at the first frequency (fo). .Iadd.     
     
     
       6.  A circuit for extracting digital data from an input signal comprising: a comparator, receiving the input signal having a first frequency and a threshold voltage, comparing the input signal with the threshold voltage and providing an output;   a first circuit, coupled to the comparator, for sampling the output of the comparator at a frequency controlled by a first clock signal;   a threshold voltage generation circuit including: an up/down counter, coupled to the output of the comparator, and operating at a second frequency to provide an output, the second frequency being a multiple greater than the first frequency; and   a digital-to-analog converter, coupled between the comparator and the up/down counter, receiving the output of the up/down counter and providing the threshold voltage; and     a phase adjusting circuit including: an edge detector, coupled to the comparator, receiving the output of the comparator and providing an output; and   a divider, coupled to the edge detector, responsive to the output of the edge detector and operating at the second frequency for producing the first clock signal at the first frequency having a phase adjusted in response to the output of the edge detector..Iaddend..Iadd.7. A circuit as claimed in claim 6 further including a digital filter coupled between the comparator and the first circuit, receiving the output of the comparator, filtering the output of the comparator, and providing the filtered comparator output to the first circuit..Iaddend..Iadd.8. A circuit as claimed in claim 7 wherein the first circuit includes a     
     
     
        flip-flop..Iaddend..Iadd.9.  A circuit as claimed in claim 8 wherein the digital filter includes a plurality of flip-flops connected in cascade and a majority detection logic circuit, coupled to each flip-flop..Iaddend..Iadd.10. Circuitry for use with a digital data extraction circuit including a comparator for comparing an input signal having a first frequency with a threshold voltage and providing an output signal, and a first circuit for sampling the output of the comparator at a frequency controlled by a first clock signal, the circuitry comprising: a threshold voltage generation circuit including: an up/down counter, coupled to the output of the comparator, and operating at a second frequency to provide an output, the second frequency being a multiple greater than the first frequency; and   a digital-to-analog converter, coupled between the comparator and the up/down counter, receiving the output of the up/down counter and providing the threshold voltage; and     a phase adjusting circuit including: an edge detector, coupled to the comparator, receiving the output of the comparator and providing an output; and   a divider, coupled to the edge detector, responsive to the output of the edge detector and operating at the second frequency for producing the first clock signal at the first frequency having a phase adjusted in response to the output of the edge detector..Iaddend..Iadd.11. Circuitry as claimed in claim 10 further including a digital filter, coupled between the comparator and the first circuit, receiving the output of the comparator, filtering the output of the comparator, and providing a     
     
     
        filtered comparator output to the first circuit..Iaddend..Iadd.12. Circuitry as claimed in claim 11 wherein the first circuit includes a flip-flop..Iaddend..Iadd.13. Circuitry as claimed in claim 12 wherein the digital filter includes a plurality of flip-flops connected in cascade and a majority detection logic circuit, coupled to each flip-flop..Iaddend.