Bit clock reproducing circuit

Abstract

.[.A bit clock reproducing circuit produces an output bit clock signal in response to an input clock signal but without reproducing jitter present in the input signal. A counter is supplied with a reference clock signal as a counting input, and the counter is periodically loaded, at a fixed time during each cycle of the input clock signal, with data which is a predetermined function of the state of the counter at such times..]. .Iadd.A bit clock reproducing circuit incorporates a counter for counting pulses of a clock pulse source after the arrival of an edge of a data pulse, at which time the counter is loaded with one of a number of preset values stored in a read-only memory, the contents of which are addressed by the counter output. Input data pulses are gated to an output terminal when the counter arrives at a predetermined state. Some values loaded into the counter may be the same for various different states of the counter immediately prior to the times when it is preset, and other values loaded into the counter are uniquely associated with the state of the counter at such times. .Iaddend.

We claim as our invention: 
     
       1. A bit clock reproducing circuit comprising: (a) a first input terminal for receiving input data;   (b) a second input terminal for receiving a reference clock signal;   (c) first circuit means connected with said first and second terminals and responsive to said input data and said reference clock signal for producing a control signal corresponding to the edge of said input data;   (d) counter means connected to said first circuit means and responsive to said control signal for receiving initial data, said counter means being connected to said second input terminal and responsive to said reference clock signal for producing a counting output signal;   (e) second circuit means connected to said counter means and responsive to said counting output signal for generating an output data signal .[.which is a predetermined function of said output counting signal.]. .Iadd.consisting of one of a plurality of values, one of said values being generated in response to any of a first plurality of different values of said counting output signal and others of said values each being generated in response to a corresponding one value of said counting output signal.Iaddend., said output data signal being provided to said counter means as said initial data; and   (f) .[.an.]. output .[.terminal.]. .Iadd.means connected to said counter means .Iaddend.for manifesting a bit clock signal corresponding to said counting output signal.   
     
     
       2. A bit clock reproducing circuit as claimed in claim 1, wherein said second circuit means is formed of a read only memory having address inputs of plural bits and memory outputs of plural bits, the counting output .[.signals.]. .Iadd.signal .Iaddend.of said counter means being supplied to said address inputs of said read only memory, and the memory data corresponding thereto supplied to said counter means as initial values. 
     
     
       3. A bit clock signal reproducing circuit comprising, a first flip-flop, a second flip-flop connected to the output of said first flip-flop, an .Iadd.exclusive-.Iaddend.OR gate connected to the outputs of said first and second flip-flops, a counter connected to the output of said OR gate and producing a plurality of outputs, a ROM receiving said plurality of outputs of said counter and producing a plurality of .Iadd.preset .Iaddend.outputs which are supplied to said counter, .Iadd.said preset outputs consisting of a plurality of values, one of said values being in response to any of a first plurality of different outputs of said counter and others of said values each being produced in response to or corresponding to one output of said counter, .Iaddend.an input clock pulse source terminal connected to said first and second flip-flops and to said counter, a third flip-flop receiving, as an input, a signal from said counter, an input data terminal supplying inputs to said first and third flip-flops, and an output terminal connected to the output of said third flip-flop to produce .[.said clock bit signal corresponding.]. .Iadd.signals in response to said input data and .Iaddend.to the .[.plurality of outputs of.]. .Iadd.said signal from .Iaddend.said counter. 
     
     
       4. A bit clock signal reproducing circuit means according to claim 3 wherein said ROM has address inputs of plural bits and memory outputs of plural bits with the plurality .Iadd.of .Iaddend.outputs of said counter supplied to the address inputs of said ROM and said memory outputs of said ROM being supplied to said counter. .Iadd. 
     
     
       5.  A bit clock signal reproducing circuit comprising, a first flip-flop, a second flip-flop connected to the output of said first flip-flop, an exclusive-OR gate connected to the outputs of said first and second flip-flops, a counter connected to the output of said exclusive-OR gate and producing a plurality of outputs, a ROM receiving said plurality of outputs of said counter and producing a plurality of outputs which are supplied to said counter, an input clock pulse source terminal connected to said first and second flip-flops and to said counter, a third flip-flop receiving, as an input, a signal from said counter, an input data terminal supplying inputs to said first and third flip-flops, and an output terminal connected to the output of said third flip-flop to produce signals in response to said input data and to said signal from said counter. .Iaddend.