Field programmable digital signal processing array integrated circuit

Abstract

A field programmable, digital signal processing integrated circuit is formed in a semiconductor die and includes an array of arithmetic logic (ALU) circuits. A user programmable interconnect architecture is superimposed on the array of ALU circuits. One or more interface circuits comprising digital-to-analog (D/A) converters or analog-to-digital (A/D) converters are may be provided on the integrated circuit to interface to off-chip analog input signals and provide off-chip analog output signals. Circuitry is provided to program the interconnections between the interface circuits and the ALU circuits and between individual ones of the ALU circuits, as well as to define the specific functions of the individual ALU circuits.

What is claimed is:  
     
       1. A field programmable, digital signal processing integrated circuit, comprising: 
       a plurality of input/output pads;  
       at least one analog to digital converter disposed in said integrated circuit, said at least one analog to digital converter having an analog input and a plurality of digital outputs;  
       at least one digital to analog converter disposed in said integrated circuit, said at least one digital to analog converter having a plurality of digital inputs and an analog output;  
       a plurality of ALU (arithmetic logic units) circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n-bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n-bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n-bit output byte from said ALU circuit on n output lines;  
       means for individually defining the operation to be performed by each of said ALU circuits;  
       a plurality of interconnect conductors in the integrated circuit;  
       interconnect means for making programmable connections between the interconnect conductors, said inputs and outputs of said ALU circuits, said digital inputs and outputs of said at least one analog to digital converter, said digital inputs and outputs of said at least one digital to analog converter, and said input/output pads, at least some of said interconnect means being user programmable; , the n output lines of at least one of said ALU circuits intersecting n interconnect conductors to form intersections, said n interconnect conductors connectable to the input lines of other ones of said ALU circuits;  
       user-programmable interconnect elements disposed at said intersections; and  
       means for programming ones of said user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between data on said n output lines of said at least one of said ALU circuits and said n interconnect conductors, whereby multiplication and division operations may be performed on said data by virtue of programmable interconnection.  
     
     
       2. The field programmable, digital signal processing integrated circuit of claim  1 , further including: 
       at least one PROM circuit disposed in said integrated circuit, said PROM including a plurality of address input lines and a plurality of data output lines; and 
       interconnect means for connecting selected ones of said interconnect conductors to said plurality of address input lines and said plurality of data output lines of said at least one PROM circuit.  
     
     
       3. A field programmable, digital signal processing integrated circuit, comprising: 
       a plurality of input/output pads;  
       at least one analog to digital converter disposed in said integrated circuit, said at least one analog to digital converter having an analog input and a plurality of digital outputs;  
       at least one digital to analog converter disposed in said integrated circuit, said at least one digital to analog converter having a plurality of digital inputs and an analog output;  
       a plurality of ALU circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n-bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n-bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n-bit output byte from said ALU circuit on n output lines;  
       means for individually defining the operation to be performed by each of said ALU circuits;  
       a plurality of interconnect conductors in the integrated circuit;  
       the n input lines of either of said first and second input bus of at least one of said ALU circuits intersecting n interconnect conductors in sets of ones of said interconnect conductors connectable to an output bus of another one of said ALU circuits to form intersections;  
       user-programmable interconnect elements disposed at said intersections; and  
       means for programming ones of said user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between data on said n interconnect conductors and on said n input lines of either of said first and second input bus of at  said at least one of said ALU circuits and , whereby multiplication and division operations may be performed on said data by virtue of interconnection.  
     
     
       4. A field programmable, digital signal processing integrated circuit, comprising: 
       a plurality of input/output pads;  
       at least one analog to digital converter disposed in said integrated circuit, said at least one analog to digital converter having an analog input and a plurality of digital outputs;  
       at least one digital to analog converter disposed in said integrated circuit, said at least one digital to analog converter having a plurality of digital inputs and an analog output;  
       a plurality of ALU circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n-bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n-bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n-bit output byte from said ALU circuit on n output lines;  
       means for individually defining the operation to be performed by each of said ALU circuits;  
       a plurality of interconnect conductors in the integrated circuit;  
       interconnect means for making programmable connections between the interconnect conductors, said inputs and outputs of said ALU circuits, said digital inputs and outputs of said at least one analog to digital converter, said digital inputs and outputs of said at least one digital to analog converter, and said input/output pads, at least some of said interconnect means comprising user-programmable interconnect elements;  
       said n input lines of the first input bus of at least one of said ALU circuits intersecting n interconnect conductors in first sets of ones of said interconnect conductors connectable to an output bus of another one of said ALU circuits to form first intersections;  
       first user-programmable interconnect elements disposed at said first intersections; and 
       means for programming ones of said first user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between first data on said n interconnect conductors of said first sets of said interconnect conductors and the n input lines of the first input bus of said at least one of said ALU circuits, whereby multiplication and division operations may be performed on said first data by virtue of interconnection.  
     
     
       5. The field programmable, digital signal processing integrated circuit of claim  4 , further  wherein: 
       said n input lines of the second input bus of at least one of said ALU circuits intersecting  intersect n interconnect conductors in second sets of ones of said interconnect conductors connectable to an output bus of another one of said ALU circuits to form second intersections; and further comprising: 
       second user-programmable interconnect elements disposed at said second intersections; and 
       means for programming ones of said second user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between second data on said n interconnect conductors of said second set of said interconnect conductors and the n input lines of the second input bus of said at least one of said ALU circuits, whereby multiplication and division operations may be performed on said second data by virtue of interconnection.  
     
     
       6. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         a plurality of ALU  ( arithmetic logic unit )  circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n - bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n - bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n - bit output byte from said ALU circuit on n output lines;    
       
         means for individually defining the operation to be performed by each of said ALU circuits;  
       
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means;    
         user - programmable interconnect elements at said intersections of one of said second sets of intersections; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between data on said output bus of said one of said ALU circuits and said interconnect conductors to perform multiplication and division operations by  2 m . 
     
     
       7. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         a plurality of ALU  ( arithmetic logic unit )  circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n - bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n - bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n - bit output byte from said ALU circuit on n output lines;    
       
         means for individually defining the operation to be performed by each of said ALU circuits;  
       
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means;    
         user - programmable interconnect elements at said intersections of one of said second sets of intersections; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between data on said first input bus of said one of said ALU circuits and said interconnect conductors to perform multiplication and division operations by  2 m . 
     
     
       8. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         a plurality of ALU  ( arithmetic logic unit )  circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n - bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n - bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n - bit output byte from said ALU circuit on n output lines;    
       
         means for individually defining the operation to be performed by each of said ALU circuits;  
       
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means, wherein one of said first sets of intersections having user - programmable interconnect elements at said intersections;    
         user - programmable interconnect elements at said intersections of first and second ones of first sets of intersections between said input buses of at least one of said ALU circuits and said interconnect conductors; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between data on said first input bus of said one of said ALU circuits and said interconnect conductors to perform multiplication and division operations by  2 m   , and to cause a bit shift of m places in either of the left and right directions between data on said second input bus of said one of said ALU circuits and said interconnect conductors to perform multiplication and division operations by  2 m . 
     
     
       9. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         a plurality of ALU  ( arithmetic logic unit )  circuit disposed in the integrated circuit, said at least one ALU circuit having a first input bus for supplying a first n - bit input byte to a first latch having n input lines, a second input bus for supplying a second n - bit input byte to a second latch having n input lines, an adder having a first set of n inputs connected to n outputs of said first latch and a second set of n inputs connected to n outputs of said second latch, a third latch having n inputs connected to n outputs of said adder and n outputs connected to an output bus, and a control circuit having a clock input, an enable input, an input - ready input, a first control output connected to latch control inputs of said first and second latches, and a second control output connected a latch control input of said third latch; and    
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means.   
     
     
       10. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
       
         a first multiplexer having a first set of n input lines connected to said first input bus and a second set of n input lines connected to a third input bus, n output lines, and a control input connectable to said interconnect conductors;  
       
       
         a second multiplexer having a first set of n input lines connected to said second input bus and a second set of n input lines connected to a fourth input bus, n output lines, and a control input said interconnect conductors;  
       
       
         a first inverting circuit having n inputs connected to said n outputs from said first multiplexer, n outputs connected to said n input lines of said first latch, and a control input connectable to said interconnect conductors;  
       
       
         a second inverting circuit having n inputs connected to said n outputs from said first multiplexer, n outputs connected to said n input lines of said second latch, and a control input connectable to said interconnect conductors. 
       
     
     
       11. The field programmable, digital signal processing integrated circuit of claim  10 , wherein said control circuit further includes an input- read output and a data ready output.   
     
     
       12. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
         user - programmable interconnect elements at first and second ones of said first sets of intersections between said first and second input buses of said at least one of said ALU circuits and said interconnect conductors; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places between said first input bus of said at least one of said ALU circuits and said interconnect conductors to perform a division operation by  2 m   , and to cause a bit shift of m places between said second input bus of said at least one of said ALU circuits and said interconnect conductors to perform a division operation by  2 m . 
     
     
       13. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
         user - programmable interconnect elements at first and second ones of said fourth sets of intersections, said first input bus of said at least one ALU circuit connectable to said second ones of said interconnect conductors in said first one of said fourth set of intersections, and said second input bus of said at least one ALU circuit connectable to said second ones of said interconnect conductors in said second one of said fourth set of intersections; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places between said first ones of said interconnect conductors in said first one of said fourth set of intersections and said first input bus of said at least one of said ALU circuits to perform a division operation by  2 m   , and to cause a bit shift of m places between said first ones of said interconnect conductors in said second one of said fourth set of intersections and said second input bus of said at least one of said ALU circuits to perform a division operation by  2 m . 
     
     
       14. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
         user - programmable interconnect elements at said second set of intersections between said output bus of said at least one ALU circuit and said interconnect conductors; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places between said output bus of said at least one of said ALU circuits and said interconnect conductors to perform a division operation by  2 m . 
     
     
       15. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
         user - programmable interconnect elements at one of said fourth sets of intersections, said output bus of said at least one ALU circuit connectable to said first ones of said interconnect conductors in said one of said fourth sets of intersections; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places between said output bus of said at least one of said ALU circuits and said second ones of said interconnect conductors in said one of said fourth sets of intersections to perform a division operation by  2 m . 
     
     
       16. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
         user - programmable interconnect elements at first and second ones of said first sets of intersections between said first and second input buses of said at least one of said ALU circuits and said interconnect conductors; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places between said first input bus of said at least one of said ALU circuits and said interconnect conductors to perform a multiplication operation by  2 m   , and to cause a bit shift of m places between said second input bus of said at least one of said ALU circuits and said interconnect conductors to perform a multiplication operation by  2 m . 
     
     
       17. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
         user - programmable interconnect elements at first and second ones of said fourth sets of intersections, said first input bus of said at least one ALU circuit connectable to said second ones of said interconnect conductors in said first one of said fourth set of intersections, and said second input bus of said at least one ALU circuit connectable to said second ones of said interconnect conductors in said second one of said fourth set of intersections; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places between said first ones of said interconnect conductors in said first one of said fourth set of intersections and said first input bus of said at least one of said ALU circuits to perform a multiplication operation by  2 m   , and to cause a bit shift of m places between said first ones of said interconnect conductors in said second one of said fourth set of intersections and said second input bus of said at least one of said ALU circuits to perform a multiplication operation by  2 m . 
     
     
       18. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
         user - programmable interconnect elements at said second set of intersections between said output bus of said at least one ALU circuit and said interconnect conductors; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places between said output bus of said at least one of said ALU circuits and said interconnect conductors to perform a multiplication operation by  2 m . 
     
     
       19. The field programmable, digital signal processing integrated circuit of claim  9 , further comprising: 
         user - programmable interconnect elements at one of said fourth sets of intersections, said output bus of said at least one ALU circuit connectable to said first ones of said interconnect conductors in said one of said fourth sets of intersections; and    
         means for programming ones of said user - programmable interconnect elements to cause a bit shift of m places between said output bus of said at least one of said ALU circuits and said second ones of said interconnect conductors in said one of said fourth sets of intersections to perform a multiplication operation by  2 m . 
     
     
       20. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         first, second, third and fourth ALU  ( arithmetic logic unit )  circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n - bit input byte to a first latch having n input lines, a second input bus for supplying a second n - bit input byte to a second latch having n input lines, an adder having a first set of n inputs connected to n outputs of said first latch and a second set of n inputs connected to n outputs of said second latch, a third latch having n inputs connected to n outputs of said adder and n outputs connected to an output bus, and a control circuit having a clock input, an enable input, an input - ready input, a first control output connected to latch control inputs of said first and second latches, and a second control output connected to a latch control input of said third latch;    
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means;    
       
         said first input bus of said first ALU circuit programmably connected to said plurality of interconnect conductors, said second input bus of said first ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, and said first ALU circuit connected to a clock line by said control circuit in said first ALU circuit;  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said second input bus of said first ALU circuit to perform a division operation by  2 m ;  
       
         said first input bus of said second ALU circuit programmably connected to said output bus of said first ALU circuit through said plurality of interconnect conductors, said second input bus of said second ALU circuit programmably connected to said output bus of said third ALU circuit through said plurality of interconnect conductors, and said second ALU circuit connected to said clock line by said control circuit in said second ALU circuit;  
       
         means for causing a bit shift of j places between said data on said output bus of said first ALU circuit and said first input bus of said second ALU circuit to perform a multiplication operation by  2 j ;  
         means for causing a bit shift of k places between said data on said output bus of third ALU circuit and said second input bus of said second ALU circuit to perform a multiplication operation by  2 k ;  
       
         said first input bus of said third ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, said second input bus of said third ALU circuit programmably connected to said output bus of said fourth ALU circuit through said plurality of interconnect conductors, and said third ALU circuit connected to said clock line by said control circuit in said third ALU circuit;  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said first input bus of said third ALU circuit to perform a division operation by  2 m ;  
         means for causing a bit shift of h places between said data on said output bus of said fourth ALU circuit and said second input bus of said third ALU circuit to perform a multiplication operation by  2 h ;  
       
         said first and second input buses of said fourth ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, and said fourth ALU circuit connected to said clock line by said control circuit in said fourth ALU circuit; and  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said first input bus of said fourth ALU circuit to perform a division operation by  2 m . 
     
     
       21. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         first, second, and third ALU  ( arithmetic logic unit )  circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n - bit input byte to a first latch having n input lines, a second input bus for supplying a second n - bit input byte to a second latch having n input lines, an adder having a first set of n inputs connected to n outputs of said first latch and a second set of n inputs connected to n outputs of said second latch, a third latch having n inputs connected to n outputs of said adder and n outputs connected to an output bus, and a control circuit having a clock input, an enable input, an input - ready input, a first control output connected to latch control inputs of said first and second latches, and a second control output connected to a latch control input of said third latch;    
         a memory device disposed in the integrated circuit, said memory device having a first n - bit address bus, a second n - bit address bus to a second latch having n input lines, and an output bus;    
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means;    
       
         said first input bus of said first ALU circuit programmably connected to said plurality of interconnect conductors, said second input bus of said first ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, and said first ALU circuit connected to a clock line by said control circuit in said first ALU circuit;  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said second input bus of said first ALU circuit to perform a division operation by  2 m ;  
       
         said first input bus of said second ALU circuit programmably connected to said output bus of said first ALU circuit through said plurality of interconnect conductors, said second input bus of said second ALU circuit programmably connected to said output bus of said memory device through said plurality of interconnect conductors, and said second ALU circuit connected to said clock line by said control circuit in said second ALU circuit;  
       
         means for causing a bit shift of j places between said data on said output bus of said first ALU circuit and said first input bus of said second ALU circuit to perform a multiplication operation by  2 j ;  
       
         said first input bus of said memory device programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, said second input bus of said memory device programmably connected to said output bus of said third ALU circuit through said plurality of interconnect conductors, and said memory device connected to said clock line;  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said first input bus of said PROM to perform a division operation by  2 m ;  
         means for causing a bit shift of h places between said data on said output bus of said third ALU circuit and said second input bus of said PROM to perform a multiplication operation by  2 h ;  
       
         said first and second input buses of said third ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, and said third ALU circuit connected to said clock line by said control circuit in said third ALU circuit; and  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said first and second input busses of said third ALU circuit to perform a division operation by  2 m . 
     
     
       22. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         first, second, third and fourth ALU  ( arithmetic logic unit )  circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n - bit input byte to a first latch having n input lines, a second input bus for supplying a second n - bit input byte to a second latch having n input lines, an adder having a first set of n inputs connected to n outputs of said first latch and a second set of n inputs connected to n outputs of said second latch, a third latch having n inputs connected to n outputs of said adder and n outputs connected to an output bus, and a control circuit having a clock input, an enable input, an input - ready input, an input ready  ( INR )  output, an output ready  ( OUTR )  output, a first control output connected to latch control inputs of said first and second latches, and a second control output connected to a latch control input of said third latch;    
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means;    
       
         said first input bus of said first ALU circuit programmably connected to said plurality of interconnect conductors, said second input bus of said first ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, and said first ALU circuit connected to a clock line by said control circuit in said first ALU circuit;  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said second input bus of said first ALU circuit to perform a division operation by  2 m ;  
       
         said first input bus of said second ALU circuit programmably connected to said output bus of said first ALU circuit through said plurality of interconnect conductors, said second input bus of said second ALU circuit programmably connected to said output bus of said third ALU circuit through said plurality of interconnect conductors, and said second ALU circuit connected to said OUTR outputs of said first and third ALU circuits by said control circuit in said second ALU circuit;  
       
         means for causing a bit shift of j places between said data on said output bus of said first ALU circuit and said first input bus of said second ALU circuit to perform a multiplication operation by  2 j ;  
         means for causing a bit shift of k places between said data on said output bus of third ALU circuit and said second input bus of said second ALU circuit to perform a multiplication operation by  2 k ;  
       
         said first input bus of said third ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, said second input bus of said third ALU circuit programmably connected to said output bus of said fourth ALU circuit through said plurality of interconnect conductors, and said third ALU circuit connected to said clock line by said control circuit in said third ALU circuit;  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said first input bus of said third ALU circuit to perform a division operation by  2 m ;  
         means for causing a bit shift of h places between said data on said output bus of said fourth ALU circuit and said second input bus of said third ALU circuit to perform a multiplication operation by  2 h ;  
       
         said first and second input buses of said fourth ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, and said fourth ALU circuit connected to said OUTR output of said second ALU circuit by said control circuit in said fourth ALU circuit; and  
       
         means for causing a bit shift of m places between said data on said output bus of said second ALU circuit and said first input bus of said fourth ALU circuit to perform a division operation by  2 m . 
     
     
       23. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         first, second, third and fourth ALU  ( arithmetic logic unit )  circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n - bit input byte to a first latch having n input lines, a second input bus for supplying a second n - bit input byte to a second latch having n input lines, an adder having a first set of n inputs connected to n outputs of said first latch and a second set of n inputs connected to n outputs of said second latch, a third latch having n inputs connected to n outputs of said adder and n outputs connected to an output bus, and a control circuit having a clock input, an enable input, an input - ready input, a first control output connected to latch control inputs of said first and second latches, and a second control output connected to a latch control input of said third latch;    
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means;    
       
         said first input bus of said first ALU circuit programmably connected to said plurality of interconnect conductors, said second input bus of said first ALU circuit programmably connected to said output bus of said fourth ALU circuit through said plurality of interconnect conductors, and said first ALU circuit connected to a first clock line by said control circuit in said first ALU circuit;  
       
       
         said first input bus of said second ALU circuit programmably connected to said output bus of said first ALU circuit through said plurality of interconnect conductors, said second input bus of said second ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, and said second ALU circuit connected to a second clock line by said control circuit in said second ALU circuit;  
       
         means for causing a bit shift of m places between said data on said output bus of said first ALU circuit and said first input bus of said second ALU circuit to perform a division operation by  2 m ;  
       
         said first input bus of said third ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, said second input bus of said third ALU circuit programmably connected to said output bus of said third ALU circuit through said plurality of interconnect conductors, and said third ALU circuit connected to a third clock line by said control circuit in said third ALU circuit;  
       
         means for causing a bit shift of j places between said data on said output bus of said second ALU circuit and said first input bus of said third ALU circuit to perform a division operation by  2 j ;  
       
         said first input bus of said fourth ALU circuit programmably connected to said output bus of said second ALU circuit through said plurality of interconnect conductors, said second input bus of said fourth ALU circuit programmably connected to said output bus of said third ALU circuit through said plurality of interconnect conductors, and said fourth ALU circuit connected to a fourth clock line by said control circuit in said fourth ALU circuit; and  
       
         means for causing a bit shift of k places between said data on said output bus of said second ALU circuit and said first input bus of said fourth ALU circuit to perform a multiplication operation by  2 k . 
     
     
       24. A field programmable, digital signal processing integrated circuit, comprising: 
       
         a plurality of input/output pads;  
       
         first, second, third, fourth and fifth ALU  ( arithmetic logic unit )  circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n - bit input byte to a first latch having n input lines, a second input bus for supplying a second n - bit input byte to a second latch having n input lines, an adder having a first set of n inputs connected to n outputs of said first latch and a second set of n inputs connected to n outputs of said second latch, a third latch having n inputs connected to n outputs of said adder and n outputs connected to an output bus, and a control circuit having a clock input, an enable input, an input - ready input, a first control output connected to latch control inputs of said first and second latches, and a second control output connected to a latch control input of said third latch;    
         a plurality of interconnect conductors in the integrated circuit, said plurality of interconnect conductors forming first sets of intersections with said input busses of said ALU circuits, second sets of intersections with said output busses of said ALU circuits, and third sets of intersections with input/output pads, and first ones of said plurality of interconnect conductors forming fourth sets of intersections with second ones of said plurality of interconnect conductors, at least some of said first, second, third and fourth sets of intersections being programmable by user - programmable interconnect means;    
       
         said first input bus of said first ALU circuit programmably connected to said plurality of interconnect conductors, said second input bus of said first ALU circuit programmably connected to said output bus of said fifth ALU circuit through said plurality of interconnect conductors, and said first ALU circuit connected to a first clock line by said control circuit in said first ALU circuit;  
       
       
         said first input bus of said second ALU circuit programmably connected to said output bus of said first ALU circuit through said plurality of interconnect conductors, said second input bus of said second ALU circuit programmably connected to said output bus of said fourth ALU circuit through said plurality of interconnect conductors, and said second ALU circuit connected to a second clock line by said control circuit in said second ALU circuit;  
       
         means for causing a bit shift of m places between said data on said output bus of said fourth ALU circuit and said second input bus of said second ALU circuit to perform a multiplication operation by  2 m ;  
       
         said first input bus of said third ALU circuit programmably connected to said output bus of said fourth ALU circuit through said plurality of interconnect conductors, said second input bus of said third ALU circuit programmably connected to said output bus of said fourth ALU circuit through said plurality of interconnect conductors, and said third ALU circuit connected to said second clock line by said control circuit in said third ALU circuit;  
       
         means for causing a bit shift of j places between said data on said output bus of said fourth ALU circuit and said first input bus of said third ALU circuit to perform a division operation by  2 j ;  
       
         said first input bus of said fifth ALU circuit programmably connected to said plurality of interconnect conductors, said second input bus of said fifth ALU circuit programmably connected to said output bus of said fourth ALU circuit through said plurality of interconnect conductors, and said fifth ALU circuit connected to said second clock line by said control circuit in said fifth ALU circuit; and  
       
         means for causing a bit shift of k places between said data on said output bus of said fourth ALU circuit and said second input bus of said fifth ALU circuit to perform a division operation by  2 k .