Apparatus for serial reading and writing of random access memory arrays

Abstract

A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.

What is claimed is:  
     
       1. Serially programmable random access memory comprising: 
       at least one random access memory array including:  
       a plurality of random access memory bits,  
       a plurality of data input lines for entering data to be stored in said random access memory array,  
       a plurality of address input lines and an address decoder for entering address information indicating in a write mode in which of said plurality of random access memory bits said data to be stored are to be stored, and for indicating in a read mode which of said plurality of random access memory bits are to be output from said random access memory array, and  
       a read/write control input, said random access memory array being in a read mode when a read/write control signal applied to said read/write control input is in a first logic state and being in a write mode when said read/write control signal applied to said read/write control input is in a second logic state;  
       for each said at least one random access memory array, a set of input/programming registers connected to said data input lines, said address input lines and said read/write control input for inputting programming data for said random access memory array, said programming data including said address information and a registered control signal to be applied to said read/write control input, and including said data to be written when said input/programming registers are used for writing, said input/programming registers being chained together such that said programming data can be entered serially into said registers; and  
       a read/write control circuit for selectively operating said at least one random access memory array in one of (a) a first mode in which said random access memory array is in one of (i) a read mode, and (ii) a write mode, regardless of said registered control signal, and (b) a second mode in which said random access memory array is in one of (i) a read mode, and (ii) a write mode, under control of said registered control signal.  
     
     
       2. The serially programmable random access memory of claim  1 , wherein: 
       said at least one random access memory array comprises a plurality of said random access memory arrays; said serially programmable random access memory further comprising:  
       a corresponding plurality of said at least one set of input registers.  
     
     
       3. The serially programmable random access memory of claim  2  wherein said plurality of sets of input registers are chained together for serial input of said programming data for said plurality of said random access memory arrays. 
     
     
       4. The serially programmable random access memory of claim  1  wherein said at least one random access memory array comprises static random access memory. 
     
     
       5. The serially programmable random access memory of claim  1  wherein said read/write control circuit comprises a selector circuit having: 
       a first input connected to one of said input registers corresponding to said registered control signal;  
       a second input for a read/write mode selection signal; and  
       a third input for a read/write option signal; wherein:  
       when said read/write option signal is in a first logic state, said read/write control circuit selects said first input as said read/write control input; and  
       when said read/write option signal is in a second logic state, said read/write control circuit selects said second input as said read/write control input.  
     
     
       6. The serially programmable random access memory of claim  5  wherein said selector circuit comprises a multiplexer. 
     
     
       7. The serially programmable random access memory of claim  5  further comprising: 
       a first input pin for said programming data;  
       a second input pin for said read/write option signal; and  
       a third input pin for said read/write mode selection signal.  
     
     
       8. The serially programmable random access memory of claim  1  wherein: 
       said at least one random access memory array further comprises a plurality of data output lines for outputting data stored in said random access memory array; said serially programmable random access memory further comprising:  
       for each said at least one random access memory array, a set of output registers connected to said data output lines for, when said at least one random access memory array is operated in a read mode, outputting from said random access memory array said data stored in said random access memory array, said output registers being chained together such that said data stored in said random access memory array can be output serially from said registers.  
     
     
       9. The serially programmable random access memory of claim  8  wherein: 
       said at least one random access memory array comprises a plurality of said random access memory arrays; said serially programmable random access memory further comprising:  
       a corresponding plurality of said at least one set of output registers.  
     
     
       10. The serially programmable random access memory of claim  9  wherein said plurality of sets of output registers are chained together for serial output of said data stored in said plurality of random access memory arrays. 
     
     
       11. A programmable logic device comprising a plurality of configurable logic circuits, serially programmable random access memory, and interconnect resource connecting said configurable logic circuits and said serially programmable random access memory, said serially programmable random access memory comprising: 
       at least one random access memory array including:  
       a plurality of random access memory bits,  
       a plurality of data input lines for entering data to be stored in said random access memory array,  
       a plurality of address input lines and an address decoder for entering address information indicating in a write mode in which of said plurality of random access memory bits said data to be stored are to be stored, and for indicating in a read mode which of said plurality of random access memory bits are to be output from said random access memory, and  
       a read/write control input, said random access memory array being in a read mode when a read/write control signal applied to said read/write control input is in a first logic state and being in a write mode when said read/write control signal applied to said read/write control input is in a second logic state;  
       for each said at least one random access memory array, a set of input/programming registers connected to said data input lines, said address input lines and said read/write control input for inputting programming data for said random access memory array, said programming data including said address information and a registered control signal to be applied to said read/write control input, and including said data to be written when said input/programming registers are used for writing, said input/programming registers being chained together such that said programming data can be entered serially into said registers; and  
       a read/write control circuit for selectively operating said at least one random access memory array in one of (a) a first mode in which said random access memory array is in one of (i) a read mode, and (ii) a write mode, regardless of said registered control signal, and (b) a second mode in which said random access memory array is in one of (i) a read mode, and (ii) a write mode, under control of said registered control signal.  
     
     
       12. The programmable logic device of claim  11 , wherein: 
       said at least one random access memory array comprises a plurality of said random access memory arrays; said serially programmable random access memory further comprising:  
       a corresponding plurality of said at least one set of input registers.  
     
     
       13. The programmable logic device of claim  12  wherein said plurality of sets of input registers are chained together for serial input of said programming data for said plurality of said random access memory arrays. 
     
     
       14. The programmable logic device of claim  11  wherein said at least one random access memory array comprises static random access memory. 
     
     
       15. The programmable logic device of claim  11  wherein said read/write control circuit comprises a selector circuit having: 
       a first input connected to one of said input registers corresponding to said registered control signal;  
       a second input for a read/write mode selection signal; and  
       a third input for a read/write option signal; wherein:  
       when said read/write option signal is in a first logic state, said read/write control circuit selects said first input as said read/write control input; and  
       when said read/write selector signal is in a second logic state, said read/write control circuit selects said second input as said read/write control input.  
     
     
       16. The programmable logic device of claim  15  wherein said selector circuit comprises a multiplexer. 
     
     
       17. The programmable logic device of claim  15  further comprising: 
       a first input pin for said programming data;  
       a second input pin for said read/write option signal; and  
       a third input pin for said read/write mode selection signal.  
     
     
       18. The programmable logic device of claim  11  wherein: 
       said at least one random access memory array further comprises a plurality of data output lines for outputting data stored in said random access memory array; said serially programmable random access memory further comprising:  
       for each said at least one random access memory array, a set of output registers connected to said data output lines for, when said at least one random access memory array is operated in a read mode, outputting from said random access memory array said data stored in said random access memory array, said output registers being chained together such that said data stored in said random access memory array can be output serially from said registers.  
     
     
       19. The programmable logic device of claim  18  wherein: 
       said at least one random access memory array comprises a plurality of said random access memory arrays; said serially programmable random access memory further comprising:  
       a corresponding plurality of said at least one set of output registers.  
     
     
       20. The programmable logic device of claim  19  wherein said plurality of sets of output registers are chained together for serial output of said data stored in said plurality of random access memory arrays. 
     
     
       21. An apparatus comprising: 
       
         a memory array including a plurality of storage locations; and  
       
       
         a serial register, coupled to said memory array, said serial register including:  
       
       
         a first field configured to store an address corresponding to one of said plurality of memory locations in said memory array;  
       
       
         a second field configured to store control information used to control access to said memory array, said control information indicating a write operation when said control information is in a first state and a read operation when said control information is in a second state; and  
       
       
         a third field configured to store data to be written into said one of said plurality of memory locations corresponding to said address stored in said first field when said control information is in said first state. 
       
     
     
       22. The apparatus of claim  21  further comprising a clock circuit configured to generate a clock signal to clock said address, said control information, and said data into said first field, said second field and said third field, respectively, of said serial register. 
     
     
       23. The apparatus of claim  22  further comprising a control circuit coupled between said serial register and said memory array, said control circuit configured to selectively provide to said memory array either said control information from said serial register during a registered access of said memory array or a second control signal during a non- registered access of said memory array.   
     
     
       24. The apparatus of claim  23  wherein said second control signal originates from a source external to said apparatus. 
     
     
       25. An apparatus comprising: 
       
         a memory array including a plurality of memory locations; and  
       
       
         a serial register coupled to said memory array, said serial register including:  
       
       
         a first field configured to store an address corresponding to one of said plurality of memory locations in said memory array; and  
       
       
         a second field configured to store control information used to control access to said one of said plurality of memory locations in said memory array corresponding to said address in said first field of said serial register. 
       
     
     
       26. The apparatus of claim  25  further including a clock circuit which generates a clock signal used to synchronize transfer of said address and said control information into said serial register. 
     
     
       27. The apparatus of claim  25  further comprising a control circuit coupled between said serial register and said memory array, said control circuit configured to provide to said memory array either said control information in said second field of said serial register or a second control signal from a source external to said apparatus. 
     
     
       28. The apparatus of claim  27  further including a clock circuit which generates a clock signal used to synchronize transfer of said address and said control information into said serial register. 
     
     
       29. The apparatus of claim  27  wherein said control circuit is configured to provide said control information in said serial register to said memory array during a registered access of the memory array. 
     
     
       30. The apparatus of claim  27  wherein said control circuit is configured to provide said second control signal to said memory array during a non- registered access of said memory array.   
     
     
       31. The apparatus of claim  25  wherein said serial register further includes a data field which is configured to store data to be written into said memory array during a write operation. 
     
     
       32. The apparatus of claim  25  wherein said control information includes information to control a write operation to said memory array. 
     
     
       33. The apparatus of claim  25  wherein said control information includes information to control a read operation of said memory array. 
     
     
       34. The apparatus of claim  25  wherein said control circuit is a multiplexer. 
     
     
       35. The apparatus of claim  25  wherein said control information is used to control a write operation of said memory array when said control information is in a first state. 
     
     
       36. The apparatus of claim  25  wherein said control information is used to control a read operation of said memory array when said control information is in a second state. 
     
     
       37. The apparatus of claim  25  further comprising a parallel- to - serial register coupled to said memory array, said parallel - to - serial register configured to receive parallel data read from said memory array and to convert said parallel data into a serial data stream.   
     
     
       38. The apparatus of claim  25  further comprising an address decoder coupled to said serial register, said address decoder configured to decode said address stored in said first field of said serial register. 
     
     
       39. The apparatus of claim  25  wherein said memory array and serial register are provided on a programmable logic device. 
     
     
       40. The apparatus of claim  39  wherein said programmable logic device is contained in a data processing system.