High definition television receiver

Abstract

A HDTV receiver which is improved in its overall performance and is simplified in its configuration, by improving a symbol timing restoring circuit, includes a tuner for selecting a necessary channel from input signals via an antenna, an IF processing & carrier restoring portion for performing an IF process & carrier restoration from the output of the tuner, an analog-to-digital converter (ADC) for converting the output of the IF processing & carrier restoring portion into a digital signal, a timing restoring portion for restoring a timing from the output of the ADC, a 2:1 down-sampler for 2:1 down-sampling the output of the ADC, a sync detector for detecting a sync from the output of the 2:1 down-sampler, a channel equalizer for performing a channel equalization from the output of the 2:1 down-sampler, a phase controller for correcting the phase error from the output of the channel equalizer, an optimal viterbi decoder for performing a viterbi decoding operation from the output of the phase controller, a deinterleaver for dissipating the output of the optimal viterbi decoder in order to enhance the correction capability due to burst errors, an error controller for performing a Reed-Solomon decoding operation with respect to the output of the deinterleaver, and a derandomizer for releasing the output of the error controller and restoring a signal randomly formed at a transmission port reversely.

What is claimed is:  
     
       1. A  An HDTV receiver comprising: 
       a tuner for selecting a necessary channel from input signals via an antenna;  
       an IF processing & carrier restoring portion for performing an IF process & carrier restoration from the  an output of said tuner;  
       an analog-to-digital converter (ADC) for converting the  an output of said IF processing & carrier restoring portion into a digital signal;  
       a timing restoring portion for restoring said  timing from the output of said ADC;  
       a 2:1 down-sampler for 2:1 down-sampling the  an output of said ADC;  
       a sync detector for detecting a sync from the  an output of the 2:1 down-sampler;  
       a channel equalizer for performing a channel equalization from the  an output of the 2:1 down-sampler;  
       a phase controller for correcting the  a phase error from the  an output of the channel equalizer;  
       an optimal viterbi decoder for performing a viterbi decoding operation from the  an output of said phase controller;  
       a deinterleaver for dissipating the  an output of said optimal viterbi decoder in order to enhance the correction  a capability due  to correct burst errors;  
       an error controller for performing a Reed-Solomon decoding operation with respect to the  an output of said deinterleaver; and  
       a derandomizer for releasing the  an output of said error controller and restoring a signal randomly formed at a transmission port reversely.  
     
     
       2. A  An HDTV receiver as claim  1 , where said timing restoring portion comprises: 
       an FIR filter for filtering only the signal of a necessary symbol rate among the  a plurality of signals passing through said ADC;  
       a phase error detector for detecting an  a phase error (ek) from the output of said FIR filter;  
       a digital-to-analog converter (DAC) for converting again the output of said phase error detector into an analog signal;  
       a lowpass filter for lowpass-filtering the output of said DAC; and  
       a voltage controlled oscillator for varying an oscillated frequency according to the output of said lowpass filter to supply a signal required in said ADC.  
     
     
       3. A  An HDTV receiver as claim  1   2 , where said phase error detector comprises: 
       first and second ½ symbol rate delays for delaying the output of said FIR filter by ½ symbol rate;  
       an adder for adding the outputs of said second ½ symbol rate delay; and  
       a multiplier for multiplying the output of said adder with the output of said first ½ symbol rate delay to output a phase error (ek).  
     
     
       4. A digital television receiver comprising: 
       
         a tuner for selecting a channel from input signals;  
       
       
         an IF processing portion for performing an IF process from an output signal of the tuner;  
       
         an analog - to - digital converter coupled to the IF processing portion and converting an output signal from the IF processing portion into a digital signal;    
         a timing restoring portion coupled to the analog - to - digital converter and restoring a timing from an output signal of the analog - to - digital converter;    
         an N:M sampler coupled to the analog - to - digital converter and N:M sampling the output signal of the analog - to - digital converter, where N and M are integers and N is greater than M;    
       
         a sync detector coupled to the N:M sampler and detecting a sync from an output signal of the N:M sampler;  
       
       
         a channel equalizer coupled to the N:M sampler and performing a channel equalization from the output signal of the N:M sampler;  
       
       
         a phase controller coupled to the channel equalizer and correcting a phase error from an output of the channel equalizer;  
       
       
         a deinterleaver coupled to the phase controller and enhancing an error correction capability;  
       
       
         an error controller coupled to the deinterleaver and performing a decoding operation with respect to an output signal of the deinterleaver; and  
       
       
         a derandomizer coupled to the error controller and releasing an output signal of the error controller and restoring a randomly formed signal. 
       
     
     
       5. The digital television receiver according to claim  4 , wherein the tuner includes the IF processing portion. 
     
     
       6. The digital television receiver according to claim  4 , further comprising a carrier restoration portion performing carrier restoration from the output signal of the tuner. 
     
     
       7. The digital television receiver according to claim  4 , wherein the N:M sampler includes a  2 : 1  down sampler. 
     
     
       8. The digital television receiver according to claim  4 , further comprising an optimal viterbi decoder coupled to the phase controller and performing a decoding operation from the output signal of the phase controller. 
     
     
       9. The digital television receiver according to claim  8 , wherein the deinterleaver dissipates an output signal of the optimal viterbi decoder. 
     
     
       10. The digital television receiver according to claim  4 , wherein the timing restoring portion comprises: 
       
         an FIR filter for filtering a signal of a selected symbol rate among a plurality of signals input to the timing restoring portion;  
       
       
         a phase error detector for detecting a phase error from an output signal of said FIR filter;  
       
         a digital - to - analog converter for converting output signal of the phase error detector into an analog signal;    
         a low pass filter for low - pass filtering an output signal of the digital - to - analog converter; and    
         a voltage controlled oscillator for varying an oscillating frequency according to an output signal of the low pass filter to supply a signal required in the analog - to - digital converter.   
     
     
       11. The digital television receiver according to claim  10 , wherein the phase error detector comprises: 
       
         first and second {fraction ( 1 / 2 )} symbol rate delays for delaying the output signal of the FIR filter by {fraction ( 1 / 2 )} symbol rate;  
       
       
         an adder for adding the output signal of the FIR filter and an output signal of the second {fraction ( 1 / 2 )} symbol rate delay; and  
       
       
         a multiplier for multiplying an output signal of the adder with an output signal of the first {fraction ( 1 / 2 )} symbol rate delay to output the phase error. 
       
     
     
       12. The digital television receiver of claim  4 , wherein the timing restoring portion restores symbol timing to the output signal of the analog- digital converter.   
     
     
       13. A digital television receiver comprising: 
       
         an input unit receiving a television signal and generating a digital signal through at least a  2 : 1  upsampling;  
       
       
         a timing restoring portion restoring a timing from the upsampled digital signal;  
       
         a down - sampler for at least  2 : 1  down sampling the upsampled digital signal and outputting a down - sampled signal;    
         a sync detector detecting a sync from the down - sampled signal of the down - sampler;    
         a channel equalizer performing a channel equalization from the down - sampled signal of the down - sampler and outputting a channel equalized signal;    
       
         a phase controller correcting a phase error from the channel equalized signal of the channel equalizer and outputting a phase controlled signal;  
       
       
         a deinterleaver coupled to the phase controller and enhancing an error correction capability and outputting a deinterleaved signal;  
       
       
         an error controller performing a decoding operation with respect to the deinterleaved signal of the deinterleaver and outputting a decoded signal; and  
       
       
         a derandomizer releasing the decoded signal of the error controller and restoring a randomly formed signal. 
       
     
     
       14. The digital television receiver according to claim  13 , wherein the input unit comprises: 
       
         a tuner selecting a channel from input signal via an antenna;  
       
       
         an IF processing portion for performing an IF process from an output signal of the tuner;  
       
       
         a carrier restoring portion for performing a carrier restoration from the output signal of the tuner; and  
       
         an analog - to - digital converter converting an output signal of the IF processing portion into the digital signal.   
     
     
       15. The digital television receiver according to claim  14 , wherein the timing restoring portion comprises: 
       
         an FIR filter for filtering a signal of a selected symbol rate among a plurality of signals input to the timing restoring portion;  
       
       
         a phase error detector for detecting a phase error from an output signal of said FIR filter;  
       
         a digital - to - analog converter for converting output signal of the phase error detector into an analog signal;    
         a low pass filter for low - pass filtering an output signal of the digital - to - analog converter; and    
         a voltage controlled oscillator for varying an oscillating frequency according to an output signal of the low pass filter to supply a signal required in the analog - to - digital converter.   
     
     
       16. The digital television receiver according to claim  15 , wherein the phase error detector comprises: 
       
         first and second {fraction ( 1 / 2 )} symbol rate delays for delaying the output signal of the FIR filter by {fraction ( 1 / 2 )} symbol rate;  
       
       
         an adder for adding the output signal of the FIR filter and an output signal of the second {fraction ( 1 / 2 )} symbol rate delay; and  
       
       
         a multiplier for multiplying an output signal of the adder with an output signal of the first {fraction ( 1 / 2 )} symbol rate delay to output the phase error. 
       
     
     
       17. The digital television receiver of claim  14 , wherein the timing restoring portion restores symbol timing to the upsampled digital signal. 
     
     
       18. The digital television receiver of claim  17 , wherein the timing restoring portion comprises: 
       
         a filter for filtering a signal of a selected symbol rate among a plurality of signals input to the filter;  
       
       
         a phase error detector for detecting a phase error in an output signal of said filter;  
       
         a low pass filter for low - pass filtering an output signal of the phase error detector; and    
         a voltage controlled oscillator for varying an oscillating frequency supplied to the low pass filter to supply a signal required in the analog - to - digital converter.   
     
     
       19. The digital television receiver according to claim  13 , wherein the input unit comprises: 
       
         a tuner selecting a channel from an input signal via an antenna; and  
       
       
         an IF processing portion for performing an IF process from an output signal of the tuner. 
       
     
     
       20. The digital television receiver according to claim  13 , wherein the input unit comprises: 
       
         a tuner selecting a channel from input signal via an antenna;  
       
       
         an IF processing portion for performing an IF process from an output signal of the tuner; and  
       
       
         carrier restoring portion for performing a carrier restoration from the output signal of the tuner. 
       
     
     
       21. The digital television receiver according to claim  13 , further comprising an optimal viterbi decoder coupled to the phase controller and performing a decoding operation from the output signal of the phase controller. 
     
     
       22. The digital television receiver according to claim  21 , wherein the deinterleaver dissipates an output signal of the optimal viterbi decoder. 
     
     
       23. The digital television receiver of claim  13 , wherein the timing restoring portion restores symbol timing to the upsampled digital signal. 
     
     
       24. The digital television receiver of claim  13 , wherein the television signal is an  8 - VSB digital television signal.   
     
     
       25. The digital television receiver of claim  24 , wherein the input unit also receives an NTSC television signal on a same channel as the  8 - VSB digital television signal, and further wherein the timing restoring portion restores symbol timing to the upsampled digital signal.   
     
     
       26. A digital television receiver, comprising: 
       
         a tuner for selecting one channel of a plurality of channels;  
       
       
         an IF processor coupled to an output of said tuner for IF processing an output signal of the tuner;  
       
         an analog - to - digital converter coupled to an output of the IF processor for converting an output signal of the IF processor to a digital signal;    
         a timing restoring portion for controlling timing of the analog - to - digital converter;    
         an N:M downsampler coupled to the output of the analog - to - digital converter for sampling the digital signal, wherein N and M are integers and N is greater than M;    
       
         a channel equalizer coupled to an output of the N:M downsampler for channel equalizing the digital signal;  
       
       
         a phase controller coupled to an output of the channel equalizer for correcting a phase error in the digital signal;  
       
       
         a deinterleaver coupled to an output of the phase controller for enhancing a capability to correct burst errors in the digital signal;  
       
       
         an error controller coupled to an output of the deinterleaver for decoding the digital signal; and  
       
       
         a derandomizer coupled to an output of said error controller for derandomizing the digital signal. 
       
     
     
       27. The digital television receiver of claim  26 , wherein the tuner receives an  8 - VSB digital television signal in the selected channel.   
     
     
       28. The digital television receiver of claim  27 , wherein the tuner also receives an NTSC television signal on a same channel as the  8 - VSB digital television signal.   
     
     
       29. The digital television receiver of claim  26 , wherein the timing restoration portion restores symbol timing to the digital signal. 
     
     
       30. The digital television receiver of claim  26 , wherein the timing restoration portion comprises: 
         a filter coupled to the output of the analog - to - digital converter for filtering a signal of a selected symbol rate among a plurality of signals input to the filter;    
       
         a phase error detector for detecting a phase error in an output signal of said filter;  
       
         a low pass filter for low - pass filtering an output signal of the phase error detector; and    
         a voltage controlled oscillator coupled to an output of the low pass filter and providing a signal for controlling timing of the analog - to - digital converter.