Graphic processing apparatus utilizing improved data transfer to reduce memory size

Abstract

A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.

We claim:  
     
       1. A graphic processing apparatus comprising: 
       memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;  
       data processing means for specifying a row address in said memory means for retrieval of data from the memory locations at the different column addresses within the specified row of memory locations and processing of the retrieved data to generate graphic signals;  
       memory control means;  
       a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit n bits of data in parallel therebetween, where m is an integer; and  
       a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;  
       said memory control means including storage means for temporarily storing data received serially on said memory data bus from memory locations at different column addresses of the memory means row corresponding with the specified row address, and transmitting the temporarily stored data in parallel on said processor data bus to said data processing means for processing thereof to generate graphic signals.  
     
     
       2. A graphic processing apparatus comprising: memory means, including a plurality of memory locations in an array of columns, having corresponding column address, and rows, having corresponding row addresses, for storing data; 
       data processing means for specifying a row address in said memory means for writing of data in the memory locations at the different column addresses within the specified row of memory locations;  
       memory control means;  
       a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and  
       a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;  
       said memory control means including multiplexer means for multiplexing data received in parallel on said processor data bus into serial data and applying the serial data to said memory data bus for writing thereof in memory locations at different column addresses of the memory means row corresponding with the specified row address.  
     
     
       3. A graphic processing apparatus comprising: 
       memory means, including a plurality of memory locations in an array of columns having corresponding column addresses, and rows, having corresponding row addresses, for storing data;  
       data processing means for specifying a row address of memory locations in said memory means for transfer of a data word therewith;  
       memory control means;  
       a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and  
       a processor data bus having n lines and interconnecting the data processing means and the memory control meant to transmit n bits of data in parallel therebetween, where n is a multiple of m;  
       said memory control means including counter means, responsive to receipt on said processor data bus of a row address specified by said processor means to specify an n-bit data word in said memory means, for successively generating n column addresses, applying the received row address and m of the generated column addresses on said memory data bus to transfer data between said memory means and said data processor means, with the data transfer including transfer of m bits of data in parallel between said memory means and said memory control means, and transfer of n bits of data between said memory control means and said data processor means.  
     
     
       4. A graphic processing apparatus comprising: 
       memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing pixel information;  
       data processing means for specifying addresses of memory locations in said memory means for retrieval of pixel information therefrom and processing of the retrieved pixel information to generate graphic signals;  
       memory control means coupled to said memory means an said data processing means for retrieving pixel information from said memory means and applying the retrieved pixel information to said data processing means for processing thereof; and  
       output means connected to said memory control means for outputting processed pixel information to generate graphics.  
     
     
       5. A graphic processing apparatus as claimed in claim  4 , wherein the pixel information comprises multi-bit pixel information units corresponding to one pixel. 
     
     
       6. A graphic processing apparatus as claimed in claim  4 , wherein the pixel information comprises pixel information units, and wherein said memory control means includes means for selecting the number of bits in each pixel information unit. 
     
     
       7. A graphic processing apparatus as claimed in claim  4 , wherein said memory control means includes storage means for temporarily storing pixel information retrieved from said memory means. 
     
     
       8. A graphic processing apparatus comprising: 
       memory meals, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;  
       data processing means for specifying a row address in said memory means for transfer of data between the data processing means and the memory location at the different column addresses within the specified row of memory locations;  
       memory control means;  
       a memory data bus having m lines and interconnecting the memory mean and the memory control means to transmit bits of data in parallel therebetween, where m n integer; and  
       a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;  
       said memory control means including storage means for temporarily storing data received on said memory bus from memory locations at different column address of the memory location row corresponding with the specified row address and transmitting the temporarily stored data in parallel on said processor data bus to said data processing means for processing thereof, and multiplexer means for multiplexing data received in parallel on said processor data bus into serial data and applying the serial data to said serial memory data bus for writing thereof in memory locations at different column addresses of the memory location row corresponding with the specified row address.  
     
     
       9. A memory controller for controlling transfer of data between memory means for storing graphic data and a processor and between said memory means and display means, comprising: 
         m - bit terminals  ( wherein m is an integer )  connected to said memory means, for transferring data of m bits successively in a predetermined period of time between said memory means and said memory controller;    
         an n - bit interface  ( wherein n is an integer and n>m )  connected to said processor, for transferring data of n bits in parallel between said processor and said memory controller based on an indication from said processor;    
       
         at least one bit terminal connected to said display means, for transferring serial data between said display means and said memory controller;  
       
         first converting means for performing conversion between data of plural sets of m bits via said m - bit terminals and data of n bits via said n - bit interface based on an indication from said processor; and    
         second converting means for converting said data of plural sets of m bits via said m - bit terminals into said serial data.   
     
     
       10. A memory controller according to claim  9 , wherein data to be converted by said first converting means are read out plural times from said memory means within a transfer unit time successively in a predetermined period of time on the basis of addresses designated by said processor. 
     
     
       11. A memory controller according to claim  9 , wherein said first converting means includes storage means for temporarily storing graphic data sent from said memory means via said m-bit terminals. 
     
     
       12. A memory controller according to claim  9 , wherein said second converting means includes storage means for temporarily storing graphic data sent from said memory means via said m-bit terminals. 
     
     
       13. A graphic processing apparatus comprising: 
       
         a memory for storing graphic data;  
       
       
         a data processor for executing a predetermined graphic processing to generate graphic data to be stored in said memory; and  
       
       
         a memory controller for controlling transfer of data between said memory and said data processor and between said memory and a display, wherein said memory controller comprises:  
       
         m - bit terminals,  ( wherein m is an integer )  connected to said memory, for transferring data of m bits successively in a predetermined period of time between said memory and said memory controller,    
         an n - bit interface,  ( wherein n is a integer and n>m )  connected to said data processor, for transferring data of n bits in parallel between said data processor and said memory controller based on an indication from said data processor,    
       
         at least one bit terminal, connected to said display, for transferring serial data between said display and said memory controller,  
       
         first converting means for performing conversion between data of plural sets of m bits via said m - bit terminals and data of n bits via said n - bit interface based on an indication from said data processor, and    
         second converting means for converting said data of plural sets of m bits via said m - bits terminal into said serial data.   
     
     
       14. A graphic processing apparatus comprising: 
       
         a memory for storing graphic data;  
       
       
         a data processor for executing a predetermined graphic processing to generate graphic data to be stored in said memory;  
       
       
         a memory controller for controlling transfer of data between said memory and said data processor and between said memory and a display;  
       
         a first bus, having m  ( wherein m is an integer )  bits width, connected between said memory and said memory controller for transferring m bits of data in parallel; and    
         a second bus, having n  ( wherein n is an integer and n>m )  bits width, connected between said memory controller and said data processor, for transferring n bits of data in parallel,    
       
         wherein said memory controller comprises:  
       
       
         at least one bit terminal, connected to said display, for transferring serial data between said display and said memory,  
       
       
         first converting means for performing conversion between data of plural sets of m bits via said first bus and data of n bits via said second bus based on an indication from said data processor, and  
       
       
         second converting means for converting said data of plural sets of m bits via said first bus into said serial data.