Synchronous semiconductor device with discontinued functions at power down

Abstract

A synchronous semiconductor device operates in synchronism with clock signal supplied from an external unit. The synchronous semiconductor device can be set in a first mode (a CSUS mode) and a power down mode (a PD mode) as an operation mode when a predetermined external signal (a CKE signal) is in a predetermined state. The synchronous semiconductor device includes a first signal generating circuit for generating a rasz signal which may be in a first state and in a second state which permits the synchronous semiconductor device to be in a state where data is not output, a second signal generating circuit for generating a rasdz signal, a change of the rasdz signal from a first state to a second state being delayed for a delay time from a change of the rasz signal generated by the first signal generating circuit from the first state to the second state, and a power down control circuit for activating the power down mode in synchronism with the clock signal when the rasdz signal is in the second state under a condition in which the predetermined external signal is in the predetermined state, so that the synchronous semiconductor device is in the power down mode.

What is claimed is:  
     
       1. A synchronous semiconductor device  circuit operating in synchronism with a clock signal supplied from an external unit, said synchronous semiconductor device capable of being set in  and having a power down mode, the power down mode being a mode in which operations of predetermined circuits are inactivated,  said synchronous semiconductor device  circuit comprising: 
       a first signal generating means forcircuit receiving an input signal and for generatingoutputting a first internal signal based onin response to said input signal, said first internal signal having a first state which permits said synchronous semiconductor device to be in a state where data is output and a second state which permits said synchronous semiconductor device to be in a state where data is not outputan active state and an inactive state;  
       a second signal generating means forcircuit receiving said input signalfirst internal signal and for generatingoutputting a second internal signal based on said input signal , a changetransition of the second internal signal from a firstan active state to a secondan inactive state being delayed for a delay time from a changetransition of the first internal signal from the firstactive state to the secondinactive state; and  
       a power down control means, connectedcircuit, coupled to said second signal generating meanscircuit, for activating the power down mode in synchronism with the clock signal based on said second internal signal when the second internal signal is in the second state, so that said synchronous semiconductor device is in the power down modeoutputting a power down signal, which indicates the power down mode, in response to the inactive state of said second internal signal.  
     
     
       2. The synchronous semiconductor device  circuit as claimed in claim  1 , wherein said synchronous semiconductor device  circuit is a synchronous dynamic random access memory (SDRAM). 
     
     
       3. The synchronous semiconductor device  circuit as claimed in claim  2 , wherein the first internal signal generated by said first signal generating means  is used in  for a precharge operation, the first internal signal indicating one of an active and inactive states of the synchronous semiconductor device . 
     
     
       4. The synchronous semiconductor device  circuit as claimed in claim  2   6 , wherein said second signal generating means includes means for setting  the delay time at a value correspondingis responsive to a CAS latency. 
     
     
       5. A synchronous semiconductor device operating in synchronism with a clock signal supplied from an external unit, said synchronous semiconductor device capable of being set in a power down mode, the power down mode being a mode in which operations of predetermined circuits are inactivated, said synchronous semiconductor device comprising: 
       a first signal generating circuit which receives an input signal and which generates a first internal signal based on said input signal, said first internal signal having a first state which permits said synchronous semiconductor device to be in a state where data is output and a second state which permits said synchronous semiconductor device to be in a state where data is not output;  
       a second signal generating circuit which receives said input signal and which generates a second internal signal based on said input signal, a change of the second internal signal from a first state to a second state being delayed from a change of the first internal signal from the first state to the second state; and  
       a control circuit, connected to said second signal generating circuit, which activates the power down mode in synchronism with the clock signal based on said second internal signal when the second internal signal is in the second state, so that said synchronous semiconductor device is in the power down mode.  
     
     
       6. The synchronous semiconductor circuit as claimed in claim  1  further comprising: 
       
         a memory bank, wherein the first internal signal is the active state when said memory bank is activated, and the first internal signal is the inactive state when said memory is not activated. 
       
     
     
       7. The synchronous semiconductor circuit as claimed in claim  6 , wherein said power down control circuit is responsive to a clock enable signal and the second internal signal. 
     
     
       8. The synchronous semiconductor circuit as claimed in claim  6  further comprising: 
       
         an input circuit receiving an external signal, wherein in the power down mode, said input circuit is inactivated in response to the power down signal. 
       
     
     
       9. The synchronous semiconductor circuit as claimed in claim  6 , wherein the input signal of said first signal generating circuit is an active command signal. 
     
     
       10. The synchronous semiconductor circuit as claimed in claim  6 , wherein the input signal of said first signal generating circuit is a burst end signal. 
     
     
       11. The synchronous semiconductor circuit as claimed in claim  6 , wherein said synchronous semiconductor circuit has an auto- precharge mode in which a precharge operation of said memory bank is automatically executed after an operation responsive to a CAS command is completed.   
     
     
       12. The synchronous semiconductor circuit as claimed in claim  11 , wherein the precharge operation is initiated in response to the inactive state of the first internal signal. 
     
     
       13. The synchronous semiconductor circuit as claimed in claim  10 , wherein the transition of the first internal signal from the active state of the inactive state is responsive to the burst end signal. 
     
     
       14. The synchronous semiconductor circuit as claimed in claim  6 , wherein the delay time is a function of a period of the clock signal. 
     
     
       15. The synchronous semiconductor circuit as claimed in claim  10 , wherein the second signal generating circuit receives the burst end signal, the transition of the second internal signal from the active state to the inactive state being response to the burst end signal. 
     
     
       16. The synchronous semiconductor circuit as claimed in claim  15 , wherein said second signal generating circuit includes a delay circuit for delaying the burst end signal and outputting a delayed burst end signal, and wherein the transition of the second internal signal from the active state to the inactive state is responsive to the delayed burst end signal. 
     
     
       17. The synchronous semiconductor circuit as claimed in claim  16 , wherein said delay circuit delays the burst end signal for n periods of the clock signal. 
     
     
       18. A synchronous semiconductor circuit having a power down mode, comprising: 
       
         an internal clock enable control circuit receiving an external clock enable signal, for outputting an internal clock enable signal;  
       
       
         a power down control circuit receiving the internal clock enable signal, for outputting a power down signal which indicates the power down mode;  
       
       
         an internal clock control circuit receiving an external clock signal and the power down signal, for outputting an internal clock signal; and  
       
       an output circuit operating in response to the internal clock signal, for outputting data, said output circuit having a high- impedance state, wherein the power down signal is activated after the output circuit becomes the high - impedance state even if the external clock enable signal is inactivated while the data is output.   
     
     
       19. The synchronous semiconductor circuit as claimed in claim  18  further comprising: 
       
         a clock suspending control circuit outputting a clock suspending signal, wherein said internal clock control circuit is responsive to the clock suspending signal. 
       
     
     
       20. The synchronous semiconductor circuit as claimed in claim  18 , wherein in the power down mode, said internal clock control circuit is inactivated in response to the power down signal. 
     
     
       21. A synchronous semiconductor circuit having a power down mode, comprising: 
       
         an internal clock enable control circuit receiving an external clock enable signal, for outputting an internal clock enable signal;  
       
       
         a power down control circuit receiving the internal clock enable signal, for outputting a power down signal which indicates the power down mode;  
       
       
         an internal clock control circuit receiving an external clock signal and the power down signal, for outputting an internal clock signal;  
       
         an output circuit operating in response to the internal clock signal, for outputting data, said output circuit having a high - impedance state; and    
         a control signal generating circuit receiving the internal clock signal, for outputting a control signal to said power down control circuit so that said power down control circuit activates the power down signal after said output circuit becomes the high - impedance state.