Semiconductor package for a semiconductor chip having centrally located bottom bond pads
Abstract
A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A semiconductor package comprising:
a semiconductor chip with a plurality of bond pads including at least one power supplying bond pad at a central portion of a bottom surface of said semiconductor chip;
a plurality of leads connected to bond pads for input/output of said bond pads, respectively, each of said leads defining an inner lead and an outer lead;
at least one bus bar connected to said at least one power supplying bond pad, said at least one bus bar defining an inner lead and an outer lead;
insulation adhesives for attaching said inner leads of each of the leads and said at least one bus bar to said bottom surface of the semiconductor chip;
metal wires for electrically connecting the inner leads of the leads and the at least one bus bar to the bond pads, respectively; and
a molding compound enveloping the semiconductor chip, and the inner leads of the leads and the bus bar with bottom surfaces of said outer leads of the leads and the bus bar exposed to outside on the bottom surface of said molding compound.
2. A semiconductor package according to claim 1 , wherein said adhesive tapes are polyimide based tapes.
3. A semiconductor package according to claim 1 , wherein said adhesive is an insulating film.
4. A semiconductor package according to claim 1 , wherein said adhesive is insulating paste.
5. A semiconductor package according to claim 1 , wherein said metal wires are gold wires.
6. A semiconductor package according to claim 1 , wherein said metal wires are aluminum wires.
7. A method of packaging a semiconductor device, comprising the steps of:
forming a plurality of contoured leads attached to a support;
attaching the plurality of contoured leads to the semiconductor chip with an insulating adhesive, wherein the contoured leads each have at least a first portion and a second portion, wherein the chip is attached at a first portion of the contoured leads, wherein the contoured leads extend away from a point where a bottom surface of the semiconductor device will be formed to provide for electrical connection of the contoured leads to the semiconductor chip;
electrically connecting the contoured leads to the semiconductor chip;
molding the semiconductor chip and the plurality of contoured leads with a resin, wherein the support is attached to the second portion of the contoured leads during the molding, wherein the semiconductor chip is completely enveloped by the resin, wherein the second portion of the contoured leads attached to the support during the molding are not covered by the resin; and
removing the support from the second portion of the contoured leads, wherein the second portion of the contoured leads is exposed to provide electrical connection points, wherein the second portion of the contoured leads is flush with the bottom surface of the semiconductor device.
8. The method of claim 7 , wherein the support comprises an adhesive tape.
9. The method of claim 7 , further comprising the step of connecting the exposed second portion of the contoured leads to a printed circuit board.
10. The method of claim 7 , wherein the contoured leads are elongated and contoured to extend away from the bottom surface of the semiconductor device.
11. The method of claim 7 , wherein the contoured leads are contoured away from the bottom surface of the semiconductor device to provide a portion for wire bonding of the contoured leads to the semiconductor chip.
12. The method of claim 7 , wherein the exposed second portions of the contoured leads comprises less than a majority portion of the area of the bottom surface.
13. The method of claim 7 , wherein the semiconductor chip has a length, wherein the contoured leads extend along the length of the semiconductor chip.
14. The method of claim 13 , wherein the contoured leads do not extend beyond the length of the semiconductor chip.
15. The method of claim 14 , wherein the semiconductor device comprises a memory device.
16. The method of claim 13 , wherein the semiconductor device comprises a memory device.
17. The method of claim 7 , wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the contoured leads are attached to the major surface by the insulating adhesive.
18. The method of claim 17 , wherein the contoured leads are attached at a central portion of the major surface.
19. The method of claim 17 , wherein the insulating adhesive comprises an insulating film.
20. The method of claim 17 , wherein the insulating adhesive comprises an insulating paste.
21. The method of claim 7 , wherein at least one of the contoured leads comprises a power supply bus bar.
22. The method of claim 21 , wherein the power supply bus bar is attached to a central portion of the semiconductor chip.
23. The method of claim 7 , wherein the contoured leads are electrically connected to the semiconductor chip with bonding wires.
24. The method of claim 7 , wherein the exposed second portions of the contoured leads are positioned on the bottom surface of the semiconductor package, wherein the exposed second portion of the contoured leads do not extend beyond the bottom surface of the semiconductor package.
25. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein the semiconductor chip has a length, wherein the leads extend along the length of the semiconductor chip, and
wherein the leads do not extend beyond the length of the semiconductor chip.
26. The method of claim 25 , further comprising the step of connecting the exposed second portion of the leads to a printed circuit board.
27. The method of claim 25 , wherein the exposed second portions of the leads are positioned on a bottom surface of the semiconductor device.
28. The method of claim 27 , wherein the leads are contoured to extend away from the bottom surface of the semiconductor device.
29. The method of claim 27 , wherein the leads are elongated and contoured to extend away from the bottom surface of the semiconductor device.
30. The method of claim 27 , wherein the leads are flush with the bottom surface of the semiconductor device.
31. The method of claim 27 , wherein the leads are contoured away from the bottom surface of the semiconductor device to provide a portion for wire bonding of the leads to the semiconductor chip.
32. The method of claim 25 , wherein the semiconductor device comprises a memory device.
33. The method of claim 25 , wherein the leads are electrically connected to the semiconductor chip with bonding wires.
34. The method of claim 25 , wherein the exposed second portions of the leads are positioned on a bottom surface of the semiconductor package, wherein the exposed second portions of the leads do not extend beyond the bottom surface of the semiconductor package.
35. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein the support comprises an adhesive tape.
36. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached to the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of lead with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points;
wherein the exposed second portions of the leads are positioned on a bottom surface of the semiconductor device, and
wherein the exposed second portions of the leads comprise less than a majority portion of the area of the bottom surface.
37. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein the semiconductor chip has a length, wherein the leads extend along the length of the semiconductor chip, and wherein the leads do not extend beyond the length of the semiconductor chip, and
wherein the semiconductor device comprises a memory device.
38. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by the insulating adhesive.
39. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by the insulating adhesive, and
wherein the leads are attached at a central portion of the major surface.
40. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by the insulating adhesive, and
wherein the insulating adhesive comprises an insulating film.
41. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of lead with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by the insulating adhesive, and
wherein the insulating adhesive comprises an insulating paste.
42. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attached the leads to a support, wherein the support is attaching to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein at least one of the leads comprises a power supply bus bar.
43. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip;
forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion;
attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads;
electrically connecting the leads to the semiconductor chip;
molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and
removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points,
wherein at least one of the leads comprises a power supply bus bar; and
wherein the power supply bus bar is attached to a central portion of the semiconductor chip.Cited by (0)
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