Memory for programmable digital filter

Abstract

The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory additionally includes a number of read amplifiers. The number of read amplifiers is equal to the number of cells of one line in order to read the bits of the addressed. The outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. Each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic. The output of each read amplifier corresponding to the most significant bit of each value is connected to the corresponding input bit line of the associated adder and to all the other most significant input bit lines.

We claimWhat is claimed is:  
     
       1. Programmable digital filter comprising an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by a plurality of lines of a plurality of one-bit cells, each being addressable by a decoder controlled by a digital signal to be filtered, each line of memory containing side by side values corresponding to the partial products of successive impulse response coefficients for a value equal to the line address, said memory furthermore comprising a number of read amplifiers equal to the number of cells of one line to read the bits of the addressed line, the outputs of said amplifiers being connected to respective parallel inputs of said adders of said arithmetical chain, characterized in that each memory line contains said values in two's-complement binary form in words which decrease in length by one bit for every increment of 2 in the characteristic of said coefficients starting from the one with lowest characteristic, and in that the output of each read amplifier corresponding to the most significant bit of each value is connected to the corresponding input bit of the associated adder and to all the other most significant input bits. 
     
     
       2. A programmable digital filter, comprising: 
         a memory receiving input values comprising a plurality of lines of one - bit cells, storing in adjacent one - bit cells values corresponding to partial products of successive impulse response coefficients for input values equal to line addresses, the cell values being in two's complement binary form in words which decrease in length by one bit for every increment of two in the characteristic of the coefficients starting from the one with lowest characteristic; and    
         a plurality of read amplifiers, equal in number to a number of one - bit cells in each line of the memory, reading the value stored in each cell of the line address corresponding to an input value, to provide filtered data.   
     
     
       3. The programmable digital filter of claim  2 , further comprising a decoder, coupled to the memory and controlled by a digital signal representing the input values to be filtered, selecting at least one of the lines of one- bit cells.   
     
     
       4. The programmable digital filter of claim  3 , further comprising an arithmetical chain of parallel adders alternated with delay elements wherein an output of each read amplifier in the plurality of read amplifiers is respectively coupled to an input of an adder in the arithmetical chain of parallel adders. 
     
     
       5. The programmable digital filter of claim  4 , wherein an output of each read amplifier in the plurality of read amplifiers corresponding to a most significant bit of each value is coupled to a corresponding input bit of the respective adder and to all other most significant input bits. 
     
     
       6. The programmable digital filter of claim  5 , wherein the filter is of symmetrical design. 
     
     
       7. The programmable digital filter of claim  5 , wherein the filter is of asymmetrical design. 
     
     
       8. The programmable digital filter of claim  5 , wherein the filter has a central coefficient. 
     
     
       9. The programmable digital filter of claim  5 , wherein the filter does not have a central coefficient. 
     
     
       10. A programmable digital filter memory, comprising a plurality of lines of adjacent one- bit cells, each line being addressable by a decoder controlled by a digital signal to be filtered, each cell containing a partial product of a successive impulse coefficient, wherein a group of the one - bit cells store data in two's - complement binary form in words that decrease in length by one bit for every increment of two in a characteristic of the coefficients for a value equal to the line address, said memory furthermore comprising a number of read amplifiers equal to the number of cells of one line to read the bits of the addressed line.   
     
     
       11. The programmable digital filter memory of claim  10 , further comprising a decoder, coupled to the plurality of lines and controlled by a digital signal to be filtered, selecting at least one of the lines of one- bit cells.   
     
     
       12. The programmable digital filter memory of claim  11 , further comprising a plurality of read amplifiers, equal in number to a number of  1 - bit cells in a line, reading the value stored in each cell.   
     
     
       13. The programmable digital filter memory of claim  10 , wherein a number of non-zero bits is given by: 
       
         N 
         b 
         =b 
         0 
         T−T 
         2 
         / 4   
       
       
         where N 
         b 
         =a number of bits  
       
       
         b 
         0 
         =a precision of a central coefficient  
       
       
         T=a number of coefficients. 
       
     
     
       14. In a programmable filter, a method comprising the steps of: 
       
         receiving a digital signal;  
       
       
         filtering a sample of the digital signal to provide a response; and  
       
         storing, in adjacent one - bit cells, values of partial products of successive impulse coefficients and the sample of the digital signal for a value equal to a line address in two's complement binary form in words that decrease in length by one bit for every increment of two in a characteristic of the impulse coefficients starting from an impulse coefficient with a lowest characteristic.