Integrated circuit protected against electrostatic discharges, with variable protection threshold

Abstract

To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.

What is claimed is:  
     
       1. An integrated circuit comprising at least a terminal to be protected and a reference terminal, and means for protecting the integrated circuit against overvoltages, said protecting means comprising 
       a diode connected between said terminals, said diode capable of being set in avalanche conduction in case an overvoltage is applied between said terminals in a direction corresponding to a reverse bias of the diode,  
       means for modifying the distribution of equipotential lines in a region where the avalanche conduction of the diode starts, said means connected to said terminal to be protected, and said means being sensitive to the rising slope of the overvoltage, in such a way that the avalanche triggering voltage is lower when the slope is steeper, and higher when the slope is less steep.  
     
     
       2. A device according to claim  1 , wherein the means to modify the distribution of the equipotential lines comprises an insulated gate completely surrounding the periphery of a region diffused in a semiconducting substrate and connected to the terminal to be protected, the gate being connected to the terminal to be protected by means of an integrating circuit. 
     
     
       3. A device according to claim  2 , wherein the gate is connected to the terminal to be protected by a resistor and is connected to the reference terminal by a capacitance. 
     
     
       4. A device according to claim  3 , wherein the capacitance is the inherent capacitance between the gate and a semiconducting substrate separated from the gate by a thin insulating layer, the substrate being connected to the reference terminal. 
     
     
       5. A device according to any of the claims  3  or  4 , wherein the resistor is a region diffused in the substrate and has a type of conductivity opposite to the substrate. 
     
     
       6. In an integrated circuit having a reference terminal and an input terminal to be protected, a structure for protecting the integrated circuit against overvoltages, comprising: 
       
         a diode connected to the input terminal, said diode being capable of being set in avalanche conduction in case an overvoltage is applied between the input terminal and the reference terminal in a direction corresponding to a reverse bias of said diode; and  
       
       
         means for altering an avalanche threshold voltage of said diode, said altering means connected to the input terminal, and said altering means responsive to a rising slope of the input voltage to lower the diode avalanche threshold voltage when the input voltage is rising relatively fast, and raising the diode avalanche threshold voltage when the input voltage is rising relatively slowly. 
       
     
     
       7. The structure of claim  6 , wherein said diode comprises a diffused region having a first conductivity type within a substrate having a second conductivity type, wherein a PN junction is formed between the diffused region and the substrate. 
     
     
       8. In an integrated circuit having a reference terminal and an input terminal to be protected, a structure for protecting the integrated circuit against overvoltages, comprising: 
       
         a diode connected to the input terminal, said diode formed from a diffused region, having a first conductivity type, within a substrate having a second conductivity type, and adjacent a surface thereof, wherein a PN junction is formed between the diffused region and the substrate, said diode further being capable of being set in avalanche conduction in case an overvoltage is applied between the input terminal and the reference terminal in a direction corresponding to a reverse bias of said diode; and  
       
       
         means for altering an avalanche threshold voltage of said diode, said altering means connected to the input terminal, and said altering means responsive to a rising slope of the input voltage to lower the diode avalanche threshold voltage when the input voltage is rising relatively fast, and raising the diode avalanche threshold voltage when the input voltage is rising relatively slowly, wherein said altering means is formed from a gate electrode overlying the PN junction adjacent to the substrate surface and separated therefrom by an insulating layer, and an integrating circuit connected to said gate and to the input terminal, wherein a charge on said gate is proportional to a change of voltage on the input terminal. 
       
     
     
       9. The structure of claim  8 , wherein said integrating circuit comprises: 
       
         a resistor connected between the input terminal and said gate; and  
       
       
         a capacitor connected between said gate and the reference terminal. 
       
     
     
       10. In an integrated circuit having a reference terminal and an input terminal to be protected, a structure for protecting the integrated circuit against overvoltages, comprising: 
       
         a doped region having a first conductivity type within a substrate having a second conductivity type, wherein a PN junction is formed between said doped region and the substrate, a portion of the PN junction extending to a surface of the substrate;  
       
       
         a first conductive element connecting the doped region to the input terminal;  
       
       
         a gate element overlying the surface of the substrate adjacent the PN junction and separated therefrom by a thin insulating layer, wherein voltage applied to said gate element alters an avalanche threshold voltage of the PN junction;  
       
       
         a resistive element connecting the input terminal to said gate element; and  
       
       
         a capacitance between said gate element and the substrate. 
       
     
     
       11. The structure of claim  10 , wherein said capacitance comprises capacitance which exists between said gate element and the substrate through the thin oxide layer. 
     
     
       12. The structure of claim  10 , wherein said resistive element comprises a conductive region of the first conductivity type formed within the substrate. 
     
     
       13. The structure of claim  10 , wherein the substrate is connected to the reference terminal. 
     
     
       14. The structure of claim  13 , wherein the reference terminal is connected to the substrate through a second doped region within the substrate which has the first conductivity type. 
     
     
       15. The structure of claim  14 , wherein the first conductivity type is N- type, and the second conductivity type is P - type, wherein the doped region, the substrate, and the second doped region together form an NPN bipolar transistor.   
     
     
       16. The structure of claim  10 , wherein said resistive element and said capacitance combine to form a circuit for integrating voltages applied to the input terminal. 
     
     
       17. The structure of claim  16 , wherein a rapidly changing voltage in a first direction is integrated to apply a gate voltage to said gate element, and wherein the gate voltage acts to lower the avalanche threshold voltage of the PN junction. 
     
     
       18. The structure of claim  17 , wherein a slowly changing voltage in the first direction is integrated to apply a lower gate voltage to said gate element, and wherein the lower gate voltage acts to raise the avalanche threshold voltage of the PN junction.