System for partitioning and testing submodule circuits of an integrated circuit

Abstract

A system for providing testing capability of individual submodules on an integrated circuit module. A test bus having a plurality of conductors is connected to selected internal ports of said submodules through three-way analog switches. Each three-way analog switch provides the capability to observe and control an internal port through combination of the ON/OFF status of two transmission gates. Test patterns for controlling the transmission gates may be provided by onboard D flip-flops which are externally programmed to control or observe ports of an individual submodule.

What is claimed is:  
     
       1. A circuit for testing analog submodules, the submodules being arranged, in an inter-connected network including a succeeding submodule which receives an input from a preceding submodule, on an integrated circuit, the testing circuit comprising: 
       (a) a test bus comprising a plurality of conductors disposed on said integrated circuit, one of said conductors terminating in an input/output connection;  
       (b) at least one 3-way analog switch, each switch comprising:  
       (i) first and second transmission gates connected together at one end,  
       (ii) an output connection connected to the one end and for connecting to an input of the succeeding submodule,  
       (iii) an input/output connection connected to said one conductor and to another end of the first transmission gate, and  
       (iv) an input connection connected  for connecting to an output of the preceding submodule and connected to another end of the second transmission gate; and  
       (c) a plurality of flip-flops, each coupled with a control input of at least one of said transmission gates, said flip-flops being arranged in series to receive on a data-in conductor a bit data pattern for configuring selected analog switches to connect an output signal of said preceding submodule to said conductor or to provide an input signal to said succeeding submodule, said flip-flops being arranged so that the first and second transmission gates within a single switch are associated with separate ones of the flip-flops.  
     
     
       2. The circuit of  claim 1  wherein said flip-flops are D-type flip-flops, each further including a respective clock input, all of the respective clock inputs being connected together. 
     
     
       3. The circuit of  claim 1 , further comprising 
       (a) at least one second 3-way analog switch having:  
       (i) first and second transmission gates connected together at one end,  
       (ii) an output connection connected to the one end and for connecting to an input of the preceding submodule,  
       (iii) an input/output connection connected to said one conductor and to another end of the first transmission gate, and  
       (iv) an input connection connected  for connecting to an output of the succeeding submodule and connected to another end of the second transmission gate; and  
       (b) wherein:  
       (i) the flip-flops comprise:  
       (A) a first pair including first first and second flip-flops; and  
       (B) a second pair including second first and second flip-flops;  
       (ii) the first transmission gate in the at least one 3-way analog switch being coupled to the first first flip-flop;  
       (iii) the second transmission gate in the at least one 3-way analog switch being coupled to the first second flip-flop;  
       (iv) the first transmission gate in the at least one second 3-way analog switch being coupled to the second first flip-flop; and  
       (v) the second transmission gate in the at least one second 3-way analog switching being coupled to the second second flip-flop.  
     
     
       4. The circuit of  claim 3 , wherein the at least one 3-way analog switch comprises a plurality of 3-way analog switches, each having a respective first transmission gate coupled to the first first flip-flop and a respective second transmission gate coupled to the first second flip-flop. 
     
     
       5. The circuit of  claim 3 , wherein the at least one second 3-way switch comprises a plurality of 3-way analog switches, each having a respective first transmission gate coupled to the second first flip-flop and a respective second transmission gate coupled to the second second flip-flop. 
     
     
       6. The circuit of  claim 5 , wherein the submodules are disposed on a common substrate along with the testing circuit; and 
       (a) the at least one 3-way analog switch comprises a plurality of 3-way analog switches, each having  
       (i) a respective first transmission gate coupled to the first first flip-flop; and  
       (ii) a respective second transmission gate coupled to the first second flip-flop; and  
       (b) the submodules are disposed on a common substrate; and 
       (c  b) the testing circuit further comprises:  
       (i) an input analog multiplexer having  
       (A) an input connected to a signal input connection of said common substrate,  
       (B) a first output to one of said test bus conductors, and 
       (C) and  a second output connected  for connecting to an input of said preceding submodule,  
        the input analog multiplexer being for selectively permitting a signal to be supplied from said signal input to said preceding submodule and said one test bus conductor;  
       (ii) an output analog multiplexer having:  
       (A) a first input connected  for connecting to an output of said succeeding submodule,  
       (B) a second input connected to said one test bus conductor, and  
       (C) an output connected to a signal output connection of said common substrate.  
     
     
       7. The circuit of  claim 1  wherein the at least one 3-way analog switch further comprises a third transmission gate coupled between the input connection of the at least one 3-way analog switch and the input/output connection of the at least one 3-way analog switch. 
     
     
       8. The circuit of  claim 1  further comprising a data input connection connected to supply  for supplying data to said flip-flops, and wherein the first and second flip-flops are serially connected, and the flip- flops are further for receiving  a test data configuration is  shifted into said  the flip-flops through said data input connection. 
     
     
       9. The circuit of  claim 1  further comprising a reset connection connected to rest  for resetting said flip-flops, said reset  and thus establishing input/output connections of said modules to a normal, non- test  configuration. 
     
     
       10. A circuit for testing analog submodules, the submodules being arranged in an interconnected network including a succeeding submodule which receives an input from a preceding submodule on an integrated circuit, the testing circuit comprising: 
       (a) a test bus comprising a plurality of conductors disposed on said integrated circuit, one of said conductors terminating in an input/output connection;  
       (b) at least one three-way analog switch, each switch comprising:  
       (i) an output connection connected  for connecting to an input of the succeeding submodule,  
       (ii) an input/output connection connected to said one conductor, and  
       (iii) an input connection connected  for connecting to an output of the preceding submodule; and  
       (c) means for configuring the at least one 3-way analog switch to assume one of the following states:  
       (i) a first state in which  for connecting the input of the succeeding module is connected  to the output of the preceding module, and not the one conductor;  
       (ii) a second state in which  for connecting the input of the succeeding module to the one conductor and not the preceding module; and  
       (iii) a third state in which  for connecting the output of the preceding module is connected  to both the input of the succeeding module and the one conductor.  
     
     
       11. The circuit of  claim 10 ,  19 , or  20 wherein each of the at least one 3-way analog switch further comprises first and second transmission gates connected together at one end. 
     
     
       12. The circuit of  claim 11  wherein the means for configuring the at least one 3-way analog switch comprises a plurality of flip-flops, each associated with at least one of said transmission gates, said flip-flops being arranged in series to receive on a data-in conductor a bit data pattern, the first and second transmission gates in each switch being associated with separate ones of the flip-flops. 
     
     
       13. The circuit of  claim 12  wherein said flip-flops are D-type flip-flops, each further including a respective clock input, all of the respective clock inputs being connected together. 
     
     
       14. The circuit of  claim 12 , wherein the at least one 3-way analog switch comprises a plurality of 3-way analog switches, the input connection of the first transmission gate in each switch being coupled with a first one of the flip-flops, the input connection of the second transmission gate in each switch being coupled with a second one of the flip-flops. 
     
     
       15. The circuit of  claim 10 ,  19 , or  20 , further comprising 
       (a) at least one second 3-way analog switch comprising  
       (i) an input connection connected  for connecting to an output of the succeeding submodule;  
       (ii) an input/output connection connected to said one conductor, ; and  
       (iii) an output connected  connection for connecting to an input of the preceding submodule; and  
       (b) means for configuring the at least one second 3-way switch to assume one of the following states  
       (i) a first state in which  for connecting the input of the preceding module is connected  to the output of the succeeding module, and not the other conductor;  
       (ii) a second state in which  for connecting the input of the preceding module is connected  to the one conductor and not the succeeding module; and  
       (iii) a third state in which  for connecting the output of the succeeding module is connected  to both the input of the preceding module and the one conductor.  
     
     
       16. The circuit of  claim 15 , wherein the at least one 3-way analog switch comprises a plurality of 3-way analog switches in parallel. 
     
     
       17. The circuit of  claim 15 , wherein the at least one second 3-way analog switch comprises a plurality of 3-way analog switches in parallel. 
     
     
       18. The circuit of  claim 11  wherein the at least one 3-way analog switch further comprises a third transmission gate coupled between the input connection of the at least one 3-way analog switch and the input/output connection of the at least one 3-way analog switch. 
     
     
       19. A test circuit for testing a subject circuit that includes at least one subject circuit input and an analog module, the test circuit using a test bus, the at least one subject circuit input being only for receiving signals and not for supplying signals, the test bus being for carrying test signals during a test mode of the subject circuit, the test bus being unused during a non- test operating mode of the subject circuit, the testing circuit comprising:    
         a )  at least one analog switch, each switch having at least three states and comprising at least the following connections    
         i )  an output connection for connecting and outputting signals to the at least one subject circuit input;    
         ii )  an input/output connection for connecting to and inputting and outputting the test signals to and from at least one wire of the test bus;    
         iii )  an input connection for receiving an input signal for the subject circuit; and    
         b )  means for configuring the at least one analog switch to assume any one of a set of states, which set includes the following states:    
         i )  a first state for connecting the input connection to the output connection, for enabling the input signal to reach the at least one subject circuit input;    
         ii )  a second state for connecting the input/output connection to the output connection, for enabling at least one test signal to reach the at least one subject circuit input; and    
         iii )  a third state for connecting the input connection to the input/output connection, for enabling the input signal to reach the test bus.   
     
     
       20. A test circuit for testing a subject circuit that includes at least one subject circuit output and an analog module, the test circuit using a test bus, the at least one subject circuit output being only for supplying signals and not for receiving signals, the test bus being for carrying test signals during a test mode of the subject circuit, the test bus being unused during a non- test operating mode of the subject circuit, the testing circuit comprising:    
         a )  at least one analog switch, each switch having at least three states and comprising at least the following connections    
         i )  an output connection for supplying an output signal from the subject circuit;    
         ii )  an input/output connection for connecting to inputting and outputting the test signals to and from at least one wire of the test bus;    
         iii )  an input connection for connecting to and receiving signals from the at least one subject circuit output;    
         b )  means for configuring the at least one switch to assume any one of a set of states, which set includes the following states:    
         i )  a first state in which the input connection is connected to the output connection for enabling the output signal to be supplied from the subject circuit;    
         ii )  a second state in which the input/output connection is connected to the output connection for enabling the test signals to reach the output connection;    
         iii )  a third state in which the input connection is connected to the input/output connection, for enabling the output signal from the subject circuit to reach the test bus.   
     
     
       21. The circuit of  claim 19  or  20  wherein 
         the switch comprises a first and at least one second sub - switches, the first switch being for coupling and decoupling the input connection and the output connection, whereby when the input and the output are coupled, the first state is achieved, and the at least one second sub - switch being for coupling and decoupling to the at least one wire of the test bus, whereby the second or third state is achieved.   
     
     
       22. The circuit of  claim 21  wherein the first and second sub- switches are coupled so that the third state uses both the first and second sub - switches.   
     
     
       23. The circuit of  claim 19  or  20  wherein the input/output connection comprises at least two bidirectional lines each coupled to a respective one of at least two wires of a test bus. 
     
     
       24. The circuit of  claim 19  or  20  wherein the analog module is part of an integrated circuit. 
     
     
       25. A testable system comprising 
       
         the test circuit of  
         claim 19 
         ;  
       
       
         the test bus; and  
       
       
         the subject circuit. 
       
     
     
       26. A testable system comprising 
       
         the test circuit of  
         claim 20 
         ;  
       
       
         the test bus; and  
       
       
         the subject circuit. 
       
     
     
       27. The test circuit of  claim 19  wherein the configuring means comprises means for transmitting a signal to the at least one analog switch for controlling the state of the at least one analog switch. 
     
     
       28. The test circuit of  claim 20  wherein the configuring means comprises means for transmitting a signal to the at least one analog switch for controlling the state of the at least one analog switch. 
     
     
       29. A testable system comprising 
       
         the circuit of  
         claim 1 
         ; and  
       
       
         the succeeding submodule. 
       
     
     
       30. A testable system comprising 
       
         the circuit of  
         claim 3 
         ;  
       
       
         the succeeding submodule; and  
       
       
         the preceding submodule. 
       
     
     
       31. A testable system comprising 
       
         the circuit of  
         claim 6 
         ;  
       
       
         the common substrate;  
       
         a plurality of submodules for connecting to inputs or outputs of the at least one  3   - way switch.   
     
     
       32. A testable system comprising 
       
         the circuit of  
         claim 10 
         ;  
       
       
         the preceding submodule;  
       
       
         the succeeding submodule. 
       
     
     
       33. A testable system comprising 
       
         the circuit of  
         claim 15 
         ;  
       
       
         the preceding submodule; and  
       
       
         the succeeding submodule. 
       
     
     
       34. The circuit of  claim 10  wherein the means for configuring comprises means for transmitting a signal to the at least one three-way switch for controlling the state of the at least one three-way switch.