Display controller and display control method for multiscan liquid crystal display

Abstract

A display controller including a frequency discriminator for attaining modes of horizontal and vertical frequencies of video signals inputted thereto according to horizontal and vertical sync signals, a memory for setting therein a screen mode matching the input video signals according to the determined frequency modes, and a horizontal timing signal generator and a vertical timing signal generator capable of arbitrarily setting horizontal and vertical display positions of the video signals. Obtaining the horizontal and vertical frequencies of the video signals, the controller conducts a control operation to generate horizontal and vertical timing signals associated with the horizontal and vertical frequencies. Even when the number of dots of the LCD panel is different from the number of dots supplied during a video display period from the input video signals, the resultant image can be presented in the central screen portion of the LCD panel.

What is claimed is:  
     
       1. A display controller of a multiscan liquid crystal display (LCD) using an LCD panel, comprising: 
       frequency discriminator means for attaining a mode of horizontal frequency and a mode of vertical frequency of video signals according to a horizontal sync signal, a vertical sync signal, and a clock signal inputted thereto;  
       memory circuit means for receiving as an input thereto data outputted from the frequency discriminator means and producing data matching a frequency inputted thereto; and  
       horizontal timing signal generator means and vertical timing signal generator means, responsive to data from the memory circuit means, for setting timing of controlling a display position of the video signals on the LCD panel.  
     
     
       2. A display controller of a multiscan LCD as claimed in  claim 1 , wherein the frequency discriminator means includes: 
       horizontal sync signal frequency discriminator means for receiving as inputs thereto the horizontal sync signal and the clock signal; and  
       vertical sync signal frequency discriminator means for receiving as inputs thereto the vertical sync signal and the horizontal sync signal,  
       the horizontal sync signal frequency discriminator means including a pixel counting section including a counter for counting the clock signal for one horizontal period of the horizontal sync signal,  
       the vertical sync signal frequency discriminator means including a line counting section including a counter for counting the horizontal sync signal for one vertical period of the vertical sync signal.  
     
     
       3. A display controller of a multiscan LCD as claimed in  claim 2 , wherein the horizontal sync signal frequency discriminator means includes a decoder for decoding a horizontal mode according to a count value of the counter. 
     
     
       4. A display controller of a multiscan LCD as claimed in  claim 2 , wherein the vertical sync signal frequency discriminator means includes a decoder means for decoding a vertical mode according to a count value of the counter. 
     
     
       5. A display controller of a multiscan LCD as claimed in  claim 1 , wherein the horizontal timing generator means includes a fine adjuster circuit means for correcting control data outputted from a memory circuit means in the frequency discriminator means. 
     
     
       6. A display controller of a multiscan LCD as claimed in  claim 1 , wherein the vertical timing generator means includes fine adjuster circuit means for correcting control data outputted from a memory circuit means in the frequency discriminator means. 
     
     
       7. A display controller of a multiscan LCD as claimed in  claim 5 , wherein the fine adjuster circuit means includes a circuit for performing an addition or a subtraction between a fine adjustment signal supplied from an external device and an output from the memory circuit means. 
     
     
       8. A display controller of a multiscan LCD as claimed in  claim 6 , wherein the fine adjuster circuit means includes a circuit for performing an addition or a subtraction between a fine adjustment signal supplied from an external device and an output from the memory circuit means. 
     
     
       9. A display control method for use with a multiscan liquid crystal display (LCD) using an LCD panel, comprising steps of: 
       attaining, according to a horizontal sync signal, a vertical sync signal, and a clock signal inputted thereto, a frequency mode of the horizontal frequency and a frequency mode of the vertical frequency of video signals;  
       referencing a look-up table according to the frequency modes and obtaining data matching a frequency inputted thereto; and  
       variably controlling, according to the data, generation of a horizontal timing signal and a vertical timing signal determining a display position of the video signals on the LCD panel.  
     
     
       10. A liquid crystal display ( LCD )  in which video signals of a plurality of signal standards can be displayed, wherein a display controller for said LCD comprises:    
       
         a pixel counter that determines a number of pixels per line of an image;  
       
       
         a line counter that determines a number of lines per image;  
       
       
         a memory that stores data corresponding to predetermined numbers of pixels and lines, which data is read out of the memory based on the number of pixels and the number of lines determined by the pixel counter and the line counter;  
       
       
         a horizontal timing signal generator and a vertical timing signal generator that set the timing by which video signals are displayed on the LCD based on data retrieved from the memory to thereby control the position of an image displayed on the LCD. 
       
     
     
       11. A liquid crystal display according to  claim 10 , wherein the pixel counter counts the number of pixels during one period of a horizontal sync signal. 
     
     
       12. The liquid crystal display according to  claim 10 , wherein the line counter counts the number of pulses of a horizontal sync signal during one period of a vertical sync signal. 
     
     
       13. The liquid crystal display according to  claim 10 , wherein the memory stores data corresponding to more than four display modes. 
     
     
       14. The liquid crystal display according to  claim 10 , further comprising an adder/subtracter to adjust the phase of a timing signal that determines the position of an image displayed on the LCD. 
     
     
       15. The liquid crystal display according to  claim 14 , further comprising an external adjusting input for receiving input data for manual adjustment of the position of an image displayed on the LCD. 
     
     
       16. A method for displaying video signals of a plurality of signal standards on a liquid crystal display ( LCD ) , comprising:    
       
         counting a number of pixels per line of an image;  
       
       
         counting a number of lines per image;  
       
       
         retrieving from a memory data corresponding to predetermined numbers of pixels and lines, which data is read out of the memory based on the counted number of pixels and the counted number of lines;  
       
       
         setting the timing by which video signals are displayed on the LCD based on data retrieved from the memory to thereby control the position of an image displayed on the LCD. 
       
     
     
       17. The method according to  claim 16 , wherein the number of pixels is counted during one period of a horizontal sync signal. 
     
     
       18. The method according to  claim 16 , wherein the number of pulses of the horizontal sync signal is counted during one period of a vertical sync signal. 
     
     
       19. The method according to  claim 16 , wherein the memory stores data corresponding to more than four display modes. 
     
     
       20. The method according to  claim 16 , further comprising adjusting the phase of a timing signal that determines the position of an image displayed on the LCD. 
     
     
       21. The method according to  claim 18 , further comprising inputting data corresponding to a manual adjustment of the position of an image displayed on the LCD. 
     
     
       22. A liquid crystal display ( LCD )  in which video signals of a plurality of signals standards can be displayed, wherein a display controller for said LCD comprises:    
       
         a first counter that determines a number of first pulses appearing during a first period of time based on a horizontal sync signal;  
       
       
         a second counter that determines a number of second pulses appearing during a second period of time based on a vertical sync signal;  
       
       
         a memory that stores data corresponding to predetermined number of first and second pulses, which data is read out of the memory based on the number of first pulses and the number of second pulses determined by the first and second counters; and  
       
       
         a timing signal generator that sets the timing in horizontal and vertical directions by which video signals are displayed on the LCD in response to the data read out of the memory to thereby control the position of an image displayed on the LCD. 
       
     
     
       23. The liquid crystal display according to  claim 22 , wherein a clock signal is used as the first pulses and said horizontal sync signal is used as the second pulses. 
     
     
       24. A method for displaying video signals of a plurality of signal standards on a liquid crystal display ( LCD ) , comprising:    
       
         counting first pulses during a first period of time based on a horizontal sync signal;  
       
       
         counting second pulses during a second period of time based on a vertical sync signal;  
       
       
         retrieving from a memory data corresponding to predetermined numbers of first and second pulses, which data is based on the counted numbers of the first and second pulses; and  
       
       
         setting the timing by which video signals are displayed on the LCD based on the data retrieved from the memory to thereby control the position of an image displayed on the LCD. 
       
     
     
       25. The method according to  claim 24 , wherein a clock signal is used as the first pulses and the horizontal sync signal is used the second pulses.