Skewless differential switch and DAC employing the same

Abstract

A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.

We claim:  
     
       1. A skewless differential switch, comprising: 
       a control input for receiving a control signal,  
       an inverter that is coupled to said control input to produce a complement of said control signal which is skewed with respect to said control signal,  
       an enable input for receiving a clock signal,  
       a plurality of storage elements, 
       a differential switch pair having complementary control inputs, 
       a pair offirst and second transfer switches responsive to said clock signal that are, each of said transfer switches having first and second switch terminals, said first switch terminals connected betweento said control inputsignal and said invertercomplement of said control signal, respectively, and said second switch terminals directly connected to respective ones of said complementary control inputs, and 
       storage elements to isolatea plurality of storage elements connected to said second switch terminals in parallel with said direct connections between said second switch terminals and said differential switch pair, said transfer switches isolating said control inputsignal and its complement from said storage elements and the complementary control inputs and, once per clock period, simultaneously transferring the control signal and its complement through their respective switches to the storage elements and the complementary control inputs, said storage elements also connected to store said signals transferred control signal and its complement and to provide de-skewed complementary output signals to said complementary control inputs having the same binary values as the control signal and its complement stored within said storage elements, and a differential switch pair having complementary control inputs that are connected to receive said pair of de-skewed complementary output signals from said storage elements so that said differential switch pair is controlled by said control input without skew.  
     
     
       2. The switch of  claim 1 , further comprising a intermediate switch pair and intermediate storage element pair that are interposed between said control input and said inverter and said pair of first and second transfer switches such that, 
       said intermediate switch pair provides a transmission path from said control input and said inverter to different ones of said intermediate storage elements in response to said clock signal, and  
       said intermediate storage elements are connected to receive said control and complement signals through said intermediate switches, store said signals and provide output signals to said pair first and second transfer switches having the same values as the respective signals stored within said intermediate storage elements.  
     
     
       3. The switch of  claim 1 , wherein said differential switch pair comprises two FETs connected in a differential configuration. 
     
     
       4. The switch of  claim 1 , wherein said differential switch pair comprises two CMOS transmission gates connected in a differential configuration. 
     
     
       5. The switch of  claim 1 , wherein said differential switch pair comprises two bipolar transistors connected in a differential configuration. 
     
     
       6. The switch of  claim 1 , wherein said storage elements comprise a pair of first and second cross-coupled weak inverters, the input and output of said first weak inverter connected to the second switch terminals of said first transfer switch and said second transfer switch, respectively, and the input and output of said second weak inverter connected to the second switch terminals of said second transfer switch and said first transfer switch, respectively. 
     
     
       7. The switch of  claim 1 , wherein said storage elements comprise capacitors. 
     
     
       8. The switch of  claim 1 , wherein each said storage element comprises a pair of cross-coupled inverters, one weak and one strong, the output of said strong inverter is connected to one of said differential control inputs and the input of said strong inverter comprises said storage element input. 
     
     
       9. The switch of  claim 8 , wherein a switch having a switch control input connects the output of said weak inverter to the input of said strong inverter, 
       said control input being connected to receive a signal which is a non-overlapping complement of said clock signal.  
     
     
       10. The switch of  claim 8 , wherein said weak inverter is a gated inverter that is enabled by a non-overlapping complement of said clock signal. 
     
     
       11. A digital to analog converter, comprising: 
       an analog output section, and 
       a digital section having a binary output and an enable output connected to provide control over said analog output section,  
       said analog output section comprising a differential switch which connects a first or second conducting terminal to a third conducting terminal thereby producing an analog output,  
       said differential switch further having a control input connected to said binary output and an enable input connected to said enable output ,  
       said differential switch further comprising,  
       an inverter connected to receive a signal from said control input and to produce a complement of said control signal,  
       control and complement inputs for receiving a control signal and a complement of said control signal which may be skewed with respect to said control signal,  
       an enable input,  
       storage elements,  
       switches connected to provide transmission paths under control of said enable input from each of said control and complement inputs to said storage elements, said storage elements also connected to store said signals and to provide de-skewed output signals having the same binary value as the respective signal stored within said storage elements, and  
       a differentially connected switches having complementary control inputs, one of said differentially connected switch control inputs being connected to receive said control signal, and the other differentially connected switch control input being connected to receive said complement signal from another of said storage elements :  
       
         a control input connected to said binary output,  
       
       
         an inverter that is coupled to said control input to produce a complement of said binary output which is skewed with respect to said binary output,  
       
       
         an enable input connected to said enable output,  
       
       
         a differential switch pair having complementary switch control inputs, said differential switch pair connecting one of two conducting terminals to a third conducting terminal depending upon the state of said complementary switch control inputs,  
       
       
         first and second transfer switches responsive to said enable input, each of said transfer switches having first and second switch terminals, said first switch terminals connected to said binary output and said complement of said binary output, respectively, and said second switch terminals directly connected to respective ones of said complementary switch control inputs, and  
       
         a plurality of storage elements connected to said second switch terminals in parallel with said direct connections between said second switch terminals and said differential switch pair, said transfer switches isolating said binary output and its complement from said storage elements and, once per clock period, simultaneously transferring the binary output and its complement through their respective switches to the storage elements and the complementary switch control inputs, said storage elements connected to store said transferred binary output and its complement and to provide de - skewed complementary output signals to said complementary switch control inputs having the same binary values as the binary output and its complement stored within said storage elements so that said differential switch pair is controlled by said binary output without skew.    
     
     
       12. The digital to analog converter of  claim 11 , wherein the said analog output is a current output. 
     
     
       13. The digital to analog converter of  claim 11 , wherein the said analog output is a voltage output. 
     
     
       14. The digital to analog converter of  claim 11 , wherein said differential switch further comprises a intermediate switch pair and intermediate storage element pair, said intermediate switch and storage element pairs interposed between said control and complement inputs and said first switch pair input and said inverter and said first and second transfer switches such that: 
       said intermediate switch pair provides a respective transmission paths from each of said inputs to one of said said control input and said inverter to respective ones of said intermediate storage elements under control of said enable input, and  
       said intermediate storage elements receive said control binary output and binary output complement signals from said inputs through said intermediate switches, store said signals and provide output signals to said first switch pair and second transfer switches having the same values as the respective signals stored within said intermediate storage elements.  
     
     
       15. The digital to analog converter of  claim 14 , wherein said differentially connected switches differential switch pair comprises two FETs connected in a differential configuration. 
     
     
       16. The switch digital to analog converter of  claim 15 , wherein said storage elements comprise a pair of cross-coupled weak inverters pair . 
     
     
       17. A differential switch, comprising: 
       a control input for receiving a single binary control signal,  
       an inverter that is coupled to said control input to produce a complement of said binary control signal which is skewed with respect to said binary control signal, 
       a latch which latches said binary control signal thereby introducing a delay between the control signal and its complement and its complement and then simultaneously transfers the binary control signal and its complement through a pair of transfer switches into a plurality of storage elements thereby eliminating the skew between the signals, and  
       a pair of differentially connected switches with two control terminals that are directly connected to the storage elements and to respective transfer switches so that said pair of differentially connected switches are controlled by the single binary control signal without skew.  
     
     
       18. A digital to analog converter comprising: 
       an analog output section,  
       a digital section having a binary output and an enable output connected to provide control of said analog output section,  
       said analog output section comprising a differential switch which connects a first or second conducting terminal to a third conducting terminal thereby producing an analog output ,  
       said differential switch further comprising, :  
       
         an inverter that is coupled to said binary output to produce a complement of said binary output which is skewed with respect to said binary output, 
       
       control and complementary inputs for receiving a control signal said binary output and its complement,  
       a latch having control and complementary inputs having two outputs which latches said control binary output and its complementary signals and simultaneously , said latch having two outputs, and transfers the binary output and its complement through a pair of transfer switches into a plurality of storage elements thereby eliminating the skew between the signals, and 
       a pair of differentially connected switches with two control terminals, said differentially connected switches connecting one of two conducting terminals to a third conducting terminal, depending upon the state of the control terminals, said control terminals being directly connected to respective ones of said latch outputs transfer switches.  
     
     
       19. The digital to analog converter of  claim 18 , wherein each of said differential switches further comprises an intermediate latch interposed between said control and complement inputs and said latch, 
       said intermediate latch connected to simultaneously latch said control and complement inputs under control of an enable input, and to provide latched control and complementary signals to said control and complementary inputs of said latch.  
     
     
       20. The digital to analog converter of  claim 19 , wherein said differentially connected switches comprise two FETs connected in a differential configuration. 
     
     
       21. A skewless differential switch, comprising: 
       
         complementary signal sources,  
       
       
         a differential switch pair having complementary control inputs,  
       
       
         a pair of transfer switches, each of said switches completing a direct transmission path between a respective one of said complementary signal sources and a respective one of said complementary control inputs when closed in response to a common clock signal, and  
       
         a plurality of storage elements connected to said complementary control inputs, said common clock signal closing said transfer switches substantially simultaneously such that said switches transfer said complementary signal sources to said complementary control inputs de - skewed, said storage elements arranged to maintain the binary values of said complementary signal sources on said complementary control inputs when said transfer switches are open.   
     
     
       22. A skewless differential switch, comprising: 
       
         first and second transfer switches, each of said switches having first and second switch terminals and arranged to provide a conductive path between said first and said second switch terminals when closed in response to a common clock signal,  
       
       
         a differential switch pair having complementary control inputs, said first terminals of said first and second transfer switches connected to receive a control bit and its complement, respectively, and said second terminals of said first and second transfer switches directly connected to respective ones of said complementary control inputs via first and second transmission paths, and  
       
       
         a plurality of storage elements connected to said second terminals of said first and second transfer switches in parallel with said first and second transmission paths, said transfer switches simultaneously transferring said control bit and its complement through their respective switches to said storage elements and said complementary control inputs in response to said common clock signal, said storage elements arranged to maintain the binary values of said transferred control bit and its complement on said complementary control inputs when said transfer switches are open. 
       
     
     
       23. The switch of  claim 22 , wherein said first and second transfer switches comprise first and second field- effect transistors  ( FETs ) , said first and second FETs' drain and source terminals providing said first and second switch terminals for said first and second switches, respectively, said FETs' gate terminals connected together to receive said common clock signal.   
     
     
       24. The switch of  claim 22 , wherein said storage elements comprise first and second cross- coupled inverters, the input and output of said first inverter connected to the second switch terminals of said first transfer switch and said second transfer switch, respectively, and the input and output of said second weak inverter connected to the second switch terminals of said second transfer switch and said first transfer switch, respectively.   
     
     
       25. The switch of  claim 22 , further comprising an inverter connected to said control bit and providing said control bit's complement.