Dynamic random access memory using imperfect isolating transistors

Abstract

Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense noes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.

We claim:  
     
       1. A dynamic random access memory (DRAM) comprising: 
       (a) a plurality of bit storage capacitors,  
       (b) a folded bit line comprised of a complementary bit line pair for receiving charge stored on one of said capacitors, having bit line capacitance,  
       (c) a sense amplifier having a pair of sense nodes for sensing a voltage differential across said sense nodes,  
       (d) high resistance controllable current leakage imperfect isolating means connecting said bit line to said sense nodes for receiving an enabling voltage from a first voltage supply for causing current leakage therethrough between said sense nodes and the bit line while maintaining high resistance,  
       (e) means for applying said enabling voltage for causing effective current to leak through the imperfect isolating means,  
       (f) means for enabling said sense amplifier and establishing full predetermined logic levels across said sense nodes,  
       (g) means applying a voltage from a second voltage supply to the imperfect isolating means for disabling said imperfect isolating means and thereby removing isolation between said sense nodes and the bit line,  
       whereby current passing through the sense amplifier to said sense nodes is enabled to charge said bit line capacitance through said imperfect isolating means to a predetermined logic voltage level.  
     
     
       2. A DRAM as defined in  claim 1  in which said imperfect isolating means is a pair of N-channel enhancement mode field effect transistors each having a source-drain circuit in series with a bit line of the bit line pair. 
     
     
       3. A DRAM as defined in  claim 2  including a voltage source applied to gates of each field effect transistor having an initial voltage level which is higher than said logic voltage level  levels and a following enabling voltage level which is equal to one of said logic level  levels, and at a later time a disabling voltage equal to the initial voltage level. 
     
     
       4. A DRAM as defined in  claim 1  in which said isolating means is a pair of P-channel enhancement mode field effect transistors each having a source-drain circuit in series with a bit line of the bit line pair. 
     
     
       5. A DRAM as defined in  claim 4  including a voltage source applied to gates of each field effect transistor having an initial voltage level which is lower than said logic voltage level  levels and a following enabling voltage level which is equal to one of said logic level  levels, and at a later time a disabling voltage equal to said initial voltage level. 
     
     
       6. A dynamic random access memory (DRAM) as defined in  claim 1 , further comprising: 
       (a) the sense amplifier having respective sense enable and restore enable inputs for providing full high and full low logic levels respectively to said sense nodes,  
       (b) power supply means for providing full high and full low logic level voltages,  
       (c) a pair of field effect transistors, one being a P-channel enhancement mode type having its source-drain circuit connected between said restore enable input and the high logic level power supply voltage and the other being an N-channel enhancement mode type having its source-drain circuit connected between the sense enable input and the low logic level power supply voltage, and  
       (d) means for providing restore and sense signals to gates of said one and other field effect transistors respectively,  
       whereby restore and sense current is supplied to said sense amplifier from said power supply means rather than from said means for providing restore and sense signals.  
     
     
       7. A dynamic random access memory (DRAM) as defined in  claim 1  comprising a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low-resistance power supply conductors extending in parallel with said row for carrying logic high level and logic low level voltages, sense amplifier enabling signal conductors extending across said chip accessible to said sense amplifiers, means for coupling sense inputs of said sense amplifiers to said power supply conductors, and means coupling said sense amplifier enabling signal conductors to enabling inputs of said means for coupling sense inputs, for enabling passage of current resulting from said logic high level and low level voltages to said sense amplifiers. 
     
     
       8. A DRAM as defined in  claim 7  in which said means for coupling sense inputs of said sense amplifiers is comprised of field effect transistors having their gates connected to said sense amplifier enabling signal conductors, said gates forming said enabling inputs. 
     
     
       9. A DRAM as defined in  claim 8  in which the sense inputs of groups of said sense amplifiers are connected together to the same field effect transistor drain terminal. 
     
     
       10. A DRAM as defined in  claim 1 , further comprising: 
       (a) the sense amplifier having sense enable and restore enable inputs for providing full high and full low logic levels respectively to said sense nodes,  
       (b) power supply means for providing full high and full low logic level voltages,  
       (c) a pair of field effect transistors, one having its source-drain circuit connected between said restore enable input and the high logic level power supply voltage and the other having its source-drain circuit connected between the sense enable input and the low logic level power supply voltage, and  
       (d) means for providing restore and sense signals to gates of said one and other field effect transistors respectively,  
       whereby restore and sense current is supplied to said sense amplifier from said power supply means rather than from said means for providing restore and sense signals.  
     
     
       11. A DRAM as defined in  claim 1 , further comprising a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low-resistance power supply conductors extending in parallel with said row for carrying logic high level and logic low level voltages, sense amplifier enabling signal conductors extending across said chip accessible to said sense amplifiers, means for coupling sense inputs of said sense amplifiers to said power supply conductors, and means coupling said sense amplifier enabling signal conductors to enabling inputs of said means for coupling sense inputs, for enabling passage of current resulting from said logic high level and low level voltages to said sense amplifiers. 
     
     
       12. A DRAM as defined in  claim 3 , further comprising a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low-resistance power supply conductors extending in parallel with said row for carrying logic high level and logic low level voltages, sense amplifier enabling signal conductors extending across said chip accessible to said sense amplifiers, means for coupling sense inputs of said sense amplifiers to said power supply conductors, and means coupling said sense amplifier enabling signal conductors to enabling inputs of said means for coupling sense inputs, for enabling passage of current resulting from said logic high level and low level voltages to said sense amplifiers. 
     
     
       13. A DRAM as defined in  claim 5 , further comprising a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers being disposed in a row, a pair of low-resistance power supply conductors extending in parallel with said row for carrying logic high level and logic low level voltages, sense amplifiers enabling signal conductors extending across said chip accessible to said sense amplifiers, means for coupling sense inputs of said sense amplifiers to said power supply conductors, and means coupling said sense amplifier enabling signal conductors to enabling inputs of said means for coupling sense inputs, for enabling passage of current resulting from said logic high level and low level voltages to said sense amplifiers. 
     
     
       14. A DRAM as defined in  claim 11  in which said means for coupling sense inputs of said sense amplifiers is comprised of field effect transistors having their gates connected to said sense amplifier enabling signal conductors, said gates forming said enabling inputs. 
     
     
       15. A DRAM as defined in  claim 14  in which the sense inputs of groups of said sense amplifiers are connected together to the same field effect transistor drain terminal. 
     
     
       16. A method of sensing in a folded bit line type of dynamic random access memory (DRAM) having a bit storage capacitor for coupling to the bit line and a sensing amplifier having sense nodes, comprising: 
       (a) imperfectly isolating the sense nodes of the sensing amplifier from the bit line using an imperfect isolating means enabled from a first voltage supply,  
       (b) coupling the capacitor to the bit line, thereby dumping its charge thereon,  
       (c) leaking said charge through the imperfect isolating means to one of the sense nodes, thereby causing a voltage differential across said sense nodes,  
       (d) sensing said differential by said sense amplifier and applying full high and low logic voltage levels respectively to said sense nodes,  
       (e) inhibiting isolation of said sense nodes from said bit line, by disabling the imperfect isolating means from a second voltage supply, whereby full logic levels are applied to complementary bit lines of said folded bit line.  
     
     
       17. A method as defined in  claim 16 , in which the isolating means is comprised of the source-drain circuits of a pair of enhancement mode field effect transistors respectively connected between the sense nodes and the complementary bit lines of the folded bit line, and  said inhibiting isolating step is comprised of applying an inhibiting voltage to gates of said field effect transistors, and the inhibiting  isolating step is comprised of changing the inhibiting voltage to the same voltage as one of said full logic voltage levels, whereby upon application of said full logic levels to said sense nodes during the sensing step, a field effect transistor having a gate voltage closest to a logic level applied to a sense node to which it is connected is caused to inhibit current flow into the bit line. 
     
     
       18. A method as defined in  claim 16  wherein the voltage differential across said sense nodes is sensed without complete isolation during a memory cycle.  
     
     
       19. A DRAM as defined in  claim 1  wherein the voltage differential across said sense nodes is sensed without complete isolation during a memory cycle.  
     
     
       20. A semiconductor memory device comprising: 
       
         a plurality of bit storage capacitors;  
       
       
         a bit line comprised of a complementary bit line pair for receiving charge stored on one of said capacitors;  
       
       
         a sense amplifier having a pair of sense nodes for sensing a voltage differential across said sense nodes and establishing full logic levels across said sense nodes; and  
       
       
         an isolator coupled between said complementary bit line pair and said sense nodes for operatively coupling a selected complementary bit line pair to said sense nodes in response to a controlling signal, the controlling signal being provided from a voltage supply having a voltage level beyond the full logic levels to restore full logic levels to the selected complementary bit line pair during a restoring portion of an active memory cycle.  
       
     
     
       21. A semiconductor memory device as claimed in  claim 20  wherein the isolator comprises n- channel transistors and the voltage supply supplies a voltage V   pp    which is greater than the full logic levels.    
     
     
       22. A semiconductor memory as claimed in  claim 21  wherein said controlling signal is a V pp    voltage during a pre - initial portion of said active memory cycle, a V   dd    logic level voltage during an initial portion of said active memory cycle, and said V   pp    voltage level again during said restoring portion of said active memory cycle.    
     
     
       23. A semiconductor memory device as claimed in  claim 20  wherein the isolator comprises p- channel transistors and the voltage supply supplies a voltage V   bb    below the full logic levels.    
     
     
       24. A semiconductor memory device as claimed in  claim 23  wherein said controlling signal is said V bb    voltage during a pre - initial portion of said active memory cycle, a V   ss    logic level voltage during an initial portion of said active memory cycle, and said V   bb    voltage level again during said restoring portion of said active memory cycle.    
     
     
       25. A semiconductor memory device as claimed in  claim 20  wherein said controlling signal attains a voltage for imperfect isolation of a selected complementary bit line pair during an initial portion of an active memory cycle.  
     
     
       26. A semiconductor memory device comprising: 
       
         a plurality of bit storage capacitors;  
       
       
         a bit line comprised of a complementary bit line pair for receiving charge stored on one of said capacitors;  
       
       
         a sense amplifier having a pair of sense nodes for sensing a voltage differential across said sense nodes and establishing full logic levels across said sense nodes; and  
       
         n - channel transistors coupled between said complementary bit line pair and said sense nodes for operatively coupling a selected complementary bit line pair to said sense nodes, a V   pp    voltage greater than the full logic levels being applied to gates of said n - channel transistors during a restoring portion of an active memory cycle.    
     
     
       27. A semiconductor memory device comprising: 
       
         plurality of bit storage capacitors;  
       
       
         a bit line comprised of a complementary bit line pair for receiving charge stored on one of said capacitors;  
       
       
         a sense amplifier having a pair of sense nodes for sensing a voltage differential across said sense nodes and establishing full logic levels across said sense nodes; and  
       
         p - channel transistors coupled between said complementary bit line pair and said sense nodes for operatively coupling a selected complementary bit line pair to said sense nodes, a V   bb    voltage less than the full logic levels being applied to gates of said p - channel transistors during a restoring portion of an active memory cycle.    
     
     
       28. A method of sensing in a dynamic random access memory ( DRAM )  having a bit line, a bit storage capacitor for coupling to the bit line, a sense amplifier having sense nodes and isolation transistors between said bit lines and sense amplifier, comprising:    
       
         coupling the capacitor to the bit line, thereby dumping its charge thereon;  
       
       
         sensing a voltage differential across said sense nodes by said sense amplifier and applying full high and low logic voltage levels respectively to said sense nodes; and  
       
       
         restoring to the bit storage capacitor the full high and low logic voltage levels by applying to said isolation transistors a controlling signal from a voltage supply having a voltage level beyond the full high and low logic voltage levels.  
       
     
     
       29. A method as claimed in  claim 28  wherein the isolating transistor is an n- channel transistor and the voltage supply supplies a voltage V   pp    which is greater than the logic level.    
     
     
       30. A method as claimed in  claim 29  wherein said controlling signal is a V pp    voltage during a pre - initial portion of said active memory cycle, a V   dd    logic level voltage during an initial portion of said active memory cycle, and said V   pp    voltage level again during said restoring portion of said active memory cycle.    
     
     
       31. A method as claimed in  claim 28  wherein the isolation transistors comprise a p- channel transistor and the voltage supply supplies a voltage V   bb    below the full logic levels.    
     
     
       32. A method as claimed in  claim 31  wherein said controlling signal is said V bb    voltage during a pre - initial portion of said active memory cycle, a V   ss    logic level voltage during an initial portion of said active memory cycle, and said V   bb    voltage level again during said restoring portion of said active memory cycle.    
     
     
       33. A method as claimed in  claim 28  wherein said controlling signal attains a voltage for imperfect isolation of a selected complementary bit line pair during an initial portion of an active memory cycle.  
     
     
       34. A method of sensing in a dynamic random access memory ( DRAM )  having a bit line, a bit storage capacitor for coupling to the bit line, a sense amplifier having sense nodes and n - channel isolation transistors between said bit lines and sense amplifier, comprising:    
       
         coupling the capacitor to the bit line, thereby dumping its charge thereon;  
       
       
         sensing a voltage differential across said sense nodes by said sense amplifier and applying full high and low logic voltage levels respectively to said sense nodes; and  
       
         restoring to the bit storage capacitor the full high and low logic by applying to said n - channel isolation transistors a V   pp    voltage greater than the full high logic level.    
     
     
       35. A method of sensing in a dynamic random access memory ( DRAM )  having a bit line, a bit storage capacitor for coupling to the bit line, a sense amplifier having sense nodes and p - channel isolation transistors between said bit lines and sense amplifier, comprising:    
       
         coupling the capacitor to the bit line, thereby dumping its charge thereon;  
       
       
         sensing a voltage differential across said sense nodes by said sense amplifier and applying full high and low logic voltage levels respectively to said sense nodes; and  
       
         restoring to the bit storage capacitor the full high and low logic voltage levels by applying to said p - channel isolation transistors a V   bb    voltage less than the full low logic voltage level.    
     
     
       36. A semiconductor memory device comprising: 
       
         a plurality of bit storage capacitors;  
       
       
         a bit line comprised of a complementary bit line pair for receiving charge stored on one of said capacitors;  
       
       
         a sense amplifier having a pair of sense nodes for sensing a voltage differential across said sense nodes and establishing full logic levels across said sense nodes; and  
       
       
         isolation means coupled between said complementary bit line pair and said sense nodes for operatively coupling a selected complementary bit line pair to said sense nodes in response to a controlling signal, the controlling signal being provided from a voltage supplying having a voltage level beyond the full logic levels to restore full logic levels to the selected complementary bit line pair during a restoring portion of an active memory cycle.