Semiconductor device manufacturing method

Abstract

With a semiconductor device manufacturing method, a lower-layer interconnection is formed on a circuit board on which a plurality of semiconductor chips are mounted. Using a screen plate with openings corresponding to desired positions on the lower-layer interconnection, screen printing of a metal paste is effected, and the printed metal paste is dried and calcined by heat treatment to form a metal pillar on the lower-layer interconnection. An insulating film covering the lower-layer interconnection and the metal pillar is formed so that the tip of the metal pillar may be exposed. An upper-layer interconnection is formed on the insulating film so that this layer may contact with the exposed tip of the metal pillar.

What is claimed is:  
     
       1. A semiconductor device manufacturing method comprising the steps of: 
       forming a lower-layer interconnection on a circuit board on which a plurality of semiconductor chips are mounted;  
       forming a metal pillar having a rounded apex on said circuit board so that the pillar may contact with at least said lower-layer interconnection, the metal pillar forming step including the step of effecting screen printing of a metal paste using a screen plate with openings corresponding to desired positions on the lower-layer interconnection and the step of drying and calcining said printed metal paste by heat treatment to form the metal pillar;  
       forming an insulating film covering said lower-layer interconnection and said metal pillar so that the tip  rounded apex of said metal pillar may be exposed; and  
       forming an upper-layer interconnection on said insulating film so that this layer may contact with the exposed tip  rounded apex of said metal pillar.  
     
     
       2. A semiconductor device manufacturing method according to  claim 1 , wherein said insulating film forming step includes the step of covering the lower-layer interconnection and said metal pillar with an interlayer insulating film, and the step of etching back the surface of said interlayer insulating film until the tip  rounded apex of said metal pillar is exposed. 
     
     
       3. A semiconductor device manufacturing method according to  claim 1 , wherein said circuit board is a semiconductor substrate, and the step of forming a lower-layer interconnection on said circuit board includes the step of forming an insulating film on the surface of said semiconductor substrate before the formation of the lower-layer interconnection. 
     
     
       4. A semiconductor device manufacturing method according to  claim 3 , wherein a specified area of said insulating film is used as a dielectric for a capacitor. 
     
     
       5. A semiconductor device manufacturing method according to  claim 1 , wherein the step of forming the lower-layer interconnection, said metal pillar, and said upper-layer interconnection on said circuit board includes effecting screen printing of a metal paste for the formation of each of these elements. 
     
     
       6. A semiconductor device manufacturing method according to  claim 1 , wherein the step of forming a lower-layer interconnection on said circuit board includes a step of forming the interconnection by depositing a barrier metal, and the step of forming said metal pillar and said lower-layer interconnection includes a step of forming these elements by effecting screen printing of a metal paste. 
     
     
       7. A semiconductor device manufacturing method according to  claim 1 , wherein the step of forming said lower-layer interconnection and said metal pillar includes a step of forming each of these elements by effecting screen printing of a metal paste, and the step of forming said upper-layer interconnection includes a step of forming the interconnection by depositing a barrier metal. 
     
     
       8. A semiconductor device manufactured according to a method comprising the steps of  claim 1 . 
     
     
       9. A multilayer interconnection substrate comprising: 
       
         a circuit board including a first interconnection layer;  
       
       
         a conductive pillar having a rounded apex on the first interconnection layer;  
       
       
         an insulating film on the circuit board; and  
       
       
         a second interconnection layer on the insulating film,  
       
       
         wherein the conductive pillar extends upward through the insulating film to the second interconnection layer, thereby forming an electrical connection with the second interconnection layer. 
       
     
     
       10. The multilayer interconnection substrate as claimed in  claim 9 , wherein the conductive pillar has a decreasing cross- sectional area along its length relative to the circuit board.   
     
     
       11. The multilayer interconnection substrate as claimed in  claim 9 , wherein the conductive pillar has a resistance of approximately  1 . 4  mΩ. 
     
     
       12. The multilayer interconnection substrate as claimed in  claim 10 , wherein the conductive pillar comprises gold. 
     
     
       13. The multilayer interconnection substrate as claimed in  claim 10 , wherein the conductive pillar has a resistance of approximately  1 . 4  mΩ. 
     
     
       14. A multilayer interconnection substrate comprising: 
       
         a circuit board including a first interconnection layer;  
       
       
         a conductive pillar, having a rounded apex, formed on the first interconnection layer, the conductive pillar being manufactured by a method comprising the steps of screen printing a metal paste using a screen plate with openings corresponding to desired positions on the first interconnection layer and drying and calcining the printed metal paste;  
       
       
         an insulating film on the circuit board; and  
       
       
         a second interconnection layer on the insulating film,  
       
       
         wherein the conductive pillar extends upward through the insulating film to the second interconnection layer, thereby forming an electrical connection with the second interconnection layer. 
       
     
     
       15. The multilayer interconnection substrate as claimed in  claim 14 , wherein the conductive pillar comprises gold. 
     
     
       16. The multilayer interconnection substrate as claimed in  claim 14 , wherein the conductive pillar has a resistance of approximately  1 . 4  mΩ. 
     
     
       17. The multilayer interconnecting substrate as claimed in  claim 8 , wherein the insulating film is made of an organic material. 
     
     
       18. The multilayer interconnecting substrate as claimed in  claim 17 , wherein the organic material is polyimide. 
     
     
       19. The multilayer interconnecting substrate as claimed in  claim 14 , wherein the insulating film is made of an organic material. 
     
     
       20. The multilayer interconnecting substrate according to  claim 19 , wherein the organic material is polyimide. 
     
     
       21. An interconnection substrate comprising: 
       
         a lower wiring layer;  
       
       
         an interlayer insulating film having an upper surface and a lower surface, the lower surface contacting the lower wiring layer; and  
       
       
         a conductive pillar having a bottom face and a top portion, the bottom face contacting the lower wiring layer, and wherein the conductive pillar penetrates the upper surface of the interlayer insulating film such that only the top portion, formed as having a rounded apex, projects through the upper surface. 
       
     
     
       22. The interconnection substrate as claimed in  claim 21 , wherein the bottom face of the conductive pillar has a greater cross- sectional area than that of the top portion of the conductive pillar.   
     
     
       23. The interconnection substrate as claimed in  claim 21 , further comprising: 
       
         an upper wiring layer having a lower surface, and contacting the upper surface of the interlayer insulating film;  
       
       
         wherein the top portion of the conductive pillar contacts at least the lower surface of the upper wiring layer, and wherein the upper wiring layer is substantially flat. 
       
     
     
       24. The multilayer interconnection substrate as claimed in  claim 21 , wherein the insulating film is made of an organic material. 
     
     
       25. The multilayer interconnection substrate as claimed in  claim 24 , wherein the organic material is polyimide. 
     
     
       26. A method for forming an interconnection substrate comprising the steps of: 
       
         forming a lower wiring layer;  
       
       
         forming a conductive pillar on the lower wiring layer by screen printing using metal paste, the conductive pillar having a top portion formed as having a rounded apex;  
       
       
         forming an interlayer insulating film having a lower surface and an upper surface, wherein the lower surface of the interlayer insulating film contacts the lower wiring layer; and  
       
       
         forming an upper wiring layer which contacts both the top portion of the conductive pillar and the upper surface of the interlayer insulating film, and wherein the upper wiring layer is substantially flat. 
       
     
     
       27. The method as claimed in  claim 26 , wherein the insulating film is made of an organic material. 
     
     
       28. The method as claimed in  claim 27 , wherein the organic material is polyimide. 
     
     
       29. A semiconductor device manufacturing method comprising the steps of: 
         forming a lower - layer interconnection on a circuit board on which a plurality of semiconductor chips are mounted;    
         forming a metal pillar on said circuit board, by screen printing using metal paste, said metal pillar having a rounded apex so that the pillar may contact with at least said lower - layer interconnection;    
         forming an insulating film covering said lower - layer interconnection and said metal pillar so that the rounded apex of said metal pillar may be exposed; and    
         forming an upper - layer interconnection on said insulating film so that this layer may contact with the exposed rounded apex of said metal pillar.   
     
     
       30. A semiconductor device manufacturing method according to  claim 29 , wherein said circuit board is a semiconductor substrate, and the step of forming a lower- layer interconnection on said circuit board includes the step of forming an insulating film on the surface of said semiconductor substrate before the formation of the lower - layer interconnection.   
     
     
       31. A semiconductor device manufacturing method according to  claim 30 , wherein a specific area of said insulating film is used as a dielectric for a capacitor. 
     
     
       32. A semiconductor device manufacturing method, comprising the steps of: 
         forming a lower - layer interconnection on a circuit board formed of one of a semiconductor substrate and an insulating substrate, a plurality of semiconductor chips being mounted on said semiconductor substrate or said insulating substrate;    
         forming a metal pillar on a predetermined area on said circuit board including said lower - layer interconnection, the metal pillar forming step including the step of effecting screen printing of a metal paste using a screen plate with openings corresponding to desired positions on the lower - layer interconnection and the step of drying and calcining said printed metal paste by heat treatment to form the metal pillar;    
         forming an insulating film covering said lower - layer interconnection and said metal pillar so that the tip of said metal pillar is exposed; and    
         forming an upper - layer interconnection on said insulating film so that the upper - layer interconnection is in contact with the exposed tip of said metal pillar,    
         wherein said screen plate is supported by a fixed frame and a movable frame which is pivoted on the fixed frame so that one end of said movable frame on the side of a free end of said screen plate is lifted upward as the movement of a squeegee used for transferring said metal paste onto lower - layer interconnection, and so that an angle between the printing surface of the circuit board and the movable frame is increased gradually, thereby bringing a gap between said printing surface of the circuit board and the screen plate to zero at the printing.   
     
     
       33. A semiconductor device manufacturing method according to  claim 1 , wherein the metal pillar is formed by said metal pillar forming step so that the metal pillar has a top portion formed as having the rounded apex and a bottom face having a greater cross- sectional area than that of the top portion.