Coding system for multiple transmitters and a single receiver

Abstract

The present invention comprises a system for remote control of garage doors and other devices wherein an extremely large number of codes are available for remote transmitters for operating the garage operator and wherein each transmitter has its own unique and permanent nonuser changeable code. The receiver at the garage door operator is capable of storing and remembering a number of different codes corresponding to different transmitters such that the receiver can be programmed so as to actuated by more than one transmitted code thus allowing two or more transmitters to actuate the same garage door operator and wherein the receiver stores the valid codes for the different transmitters.

We claim as our invention:  
     
       1. A garage door operator for a garage door comprising, a garage door operation mechanism with an output shaft connected to said garage door to open and close it, a radio receiver, a decoder connected to receive the output of said radio receiver, a microprocessor connected to receive the output of said decoder and to said garage door operation mechanism to energize it, a switch moveable between program and operate positions connected to said microprocessor to place said microprocessor in the operate or the program mode, a memory means for storing a plurality of addresses connected to said microprocessor when said switch is in the program position, a memory selection switch connected to said microprocessor, a plurality of radio transmitters with different codes, said memory selection switch setable in a first position at a time when a first one of said radio transmitters is energized so that the code of said first transmitter will be stored in said memory means and said memory selection switch setable in a second position at a time when a second one of said radio transmitters is energized so that the code of said second transmitter will be stored in said memory means, and said microprocessor placed in the operate mode when said switch is in the operate position so that either or both of said first and second radio transmitters when energized cause said microprocessor to energize said garage door operator mechanism. 
     
     
       2. A garage door operator for a garage door according to  claim 1  wherein said first and second radio transmitters when energized radiate coded signals and said microprocessor receives and compares coded signals from said first and second transmitters with coded signals stored in said memory means and said microprocessor produces a garage door operate signal if the received transmitted signal and any one of said coded signals stored in said memory means match. 
     
     
       3. A garage door operator according to  claim 2  wherein said memory selection switch has “n” positions where “n” is an integer and the codes of “n” transmitters can be stored in said memory means when said switch is in the program mode. 
     
     
       4. A garage door operator according to  claim 3  wherein the code stored in said memory means can be changed by placing said switch in the program mode and one of said plurality of transmitters is energized which has a code which differs from the code previously stored in said memory means. 
     
     
       5. A remotely controlled system comprising: 
       at least one radio frequency transmitter having a non-user changeable code for radio frequency transmitting a radio frequency transmission corresponding to the transmitter; 
       a radio frequency receiver for being adapted to receive the first-mentioned radio frequency transmission from the first-mentioned radio frequency transmitter and being adapted to receive a second radio frequency transmission from a second radio frequency transmitter having a second non-user changeable code, different from said first non-user changeable code; 
       a program mode designator for designating a program mode; 
       a memory comprising a plurality of storage locations; 
       a processor having a processor controlled code location pointer and responsive to a program mode designation by said program mode designator and the reception by said radio frequency receiver of said first-mentioned radio frequency transmission for storing a first stored code corresponding to the first-mentioned radio frequency transmitter in one of said plurality of storage locations derived from the processor controlled code location pointer, the processor responsive to said program mode designation by said program mode designator and the reception by said receiver of said second radio frequency transmission for storing a second stored code corresponding to the second radio frequency transmitter in another of said plurality of storage locations derived from the processor controlled code location pointer, and the processor responsive to an operate mode and the reception of said first-mentioned radio frequency transmission after the storage of said first stored code for providing an operate output and responsive to said operate mode and to the reception of said second radio frequency transmission after the storage of said first and second stored codes for providing an operate output. 
     
     
       6. A remotely controlled system according to  claim 5  wherein the processor comprises a microprocessor. 
     
     
       7. A remotely controlled system according to  claim 5  wherein said processor controlled code location pointer comprises a software controlled code location pointer. 
     
     
       8. A remotely controlled system according to  claim 7  wherein the processor comprises a microprocessor. 
     
     
       9. A remotely controlled system comprising: 
       a first radio frequency transmitter having a first non-user changeable code and for radio frequency transmitting a first radio frequency transmission corresponding to the first transmitter; 
       a second radio frequency transmitter having a second non-user changeable code, different from said first non-user changeable code and for radio frequency transmitting a second radio frequency transmission corresponding to the second transmitter; and 
       an operator for providing an operate output, said operator comprising: 
       a radio frequency receiver for receiving said first and said second radio frequency transmissions; 
       a program mode designator for designating a program mode;  
       
         a memory comprising a plurality of storage locations; 
       
       a processor having a software controlled code location pointer and responsive to a program mode designation by said program mode designator and the reception by said radio frequency receiver of said first radio frequency transmission for storing a first stored code corresponding to the first radio frequency transmitter in one of said plurality of storage locations derived from the software controlled code location pointer, the processor responsive to said program mode designation by said program mode designator and the reception by said receiver of said second radio frequency transmission for storing a second stored code corresponding to the second radio frequency transmitter in another of said plurality of storage locations derived from the software controlled code location pointer, and the processor responsive to an operate mode and the reception of said first radio frequency transmission after the storage of said first stored code for providing an operate output and responsive to said operate mode and to the reception of said second radio frequency transmission after the storage of said first and said second stored codes for providing an operate output. 
     
     
       10. A remotely controlled system according to  claim 9  wherein the processor comprises a microprocessor. 
     
     
       11. A remotely controlled system comprising, a radio receiver, a decoder connected to receive the output of said radio receiver, a microprocessor connected to receive the output of said decoder and to provide an operate output, a program/operate selector connected to said microprocessor to place said microprocessor in a program mode, memory means for storing a plurality of non-user changeable codes connected to said microprocessor when said program/operate selector is in the program position, a memory selector for selecting respective storage addresses in the memory means, a plurality of radio transmitters with different non-user changeable codes, said memory selector pointing to a first storage address at a time when a first one of said radio transmitters is energized so that the code of said first transmitter will be stored in said memory means in said first address and said memory selector pointing to a second storage address at a time when a second one of said radio transmitters is energized so that the code of said second transmitter will be stored in said memory means in said second address, and said microprocessor placed in the operate mode when said program/operate selector is in the operate position so that either of said first and second radio transmitters when energized cause said microprocessor to provide an operate output. 
     
     
       12. A remotely controlled system according to  claim 11  wherein said first and second radio transmitters when energized radiate coded signals and said microprocessor receives and compares coded signals from said first and second transmitters with coded signals stored in said memory means and said microprocessor produces an operate output if the received transmitted signal and any one of said coded signals stored in said memory means match. 
     
     
       13. A remotely controlled system according to  claim 11  wherein said memory selector has “n” positions where “n” is an integer and the codes of “n” transmitters can be stored in said memory means when said switch is in the program mode. 
     
     
       14. A remotely controlled system according to  claim 11  wherein the code stored in said memory means can be changed by placing said program/operate selector in the program mode and one of said plurality of transmitters is energized which has a code which differs from the code previously stored in said memory means. 
     
     
       15. A remotely controlled system according to  claim 11  wherein the memory selector comprises a software controlled code location pointer identifying a memory address. 
     
     
       16. A remotely controlled system comprising: a radio receiver, a decoder connected to receive the output of said radio receiver, a microprocessor connected to receive the output of said decoder and generate an operate output, a selector for selecting a program state connected to said microprocessor to place said microprocessor in the program mode, a memory for storing a plurality of codes connected to said microprocessor when said selector is in the program state position, a memory selector for selecting respective storage addresses in the memory, a plurality of radio transmitters with different non-user changeable codes, said memory selector being adapted to select a first storage location at a time when a first one of said radio transmitters is energized so that the code of said first transmitter will be stored in said memory in the first location and said memory selector being adapted to select a second storage location at a time when a second one of said radio transmitters is energized so that the code of said second transmitter will be stored in said memory in said second location, and said microprocessor placed in the operate mode when said selector is in the operate state so that either of said first and second radio transmitters, when energized cause said microprocessor to provide the operate output. 
     
     
       17. A remotely controlled system according to  claim 16  wherein the memory selector comprises a software controlled code location pointer identifying a memory address. 
     
     
       18. A remotely controlled system according to  claim 16  wherein said first and second radio transmitters when energized radiate coded signals and said microprocessor receives and compares coded signals from said first and second transmitters with coded signals stored in said memory and said microprocessor provides the operate output if the received transmitted signal and any one of said coded signals stored in said memory match. 
     
     
       19. A remotely controlled system according to  claim 16  wherein said memory selector has “n” states where “n” is an integer and the codes of “n” transmitters can be stored in said memory means when said selector is in the program state. 
     
     
       20. A remotely controlled system according to  claim 16  wherein the code stored in said memory can be changed by placing said selector in the program state and one of said plurality of transmitters is energized which has a code which differs from at least one of the codes previously stored in said memory. 
     
     
       21. A remotely controlled system according to  claim 17  wherein the microprocessor increments the code location pointer to select the memory addresses to store the respective transmitter codes. 
     
     
       22. A remotely controlled system comprising: a plurality of RF transmitters, each of said transmitters having its own different non- user changeable transmitter code and having an RF emitter for transmitting when energized, an RF signal carrying a code from which the transmitter code can be derived; a receiver for receiving said coded RF transmissions; a decoder for deriving a code corresponding to the transmitter code in the energized transmitter; a processor for providing in its operate mode an operate output and for providing in its program mode a derived code for storage; a mode selector connected to said processor for placing said processor in its program mode; a memory having a plurality of addresses for storing a plurality of derived codes under the control of said processor; a memory selector controlled by said processor for identifying respective ones of the memory addresses; said memory selector identifying one of the memory addresses so that the processor, when in its program mode, causes the derived code of one of the transmitters to be stored in said memory at the one memory address, and said memory selector identifying a second memory address so that the processor, when in its program mode, causes the derived code of a second transmitter to be stored in said memory at the second memory address; said processor, when in its operate mode, determining whether the derived code and one of the stored codes correspond, said processor providing an operate output in response to derived code and stored code correspondence.   
     
     
       23. A remotely controlled system in accordance with  claim 22 , wherein the processor determines whether the derived code has been previously stored in any of the memory locations and if the derived code is already stored, the processor does not cause the derived code to be stored. 
     
     
       24. A remotely controlled system in accordance with  claim 22 , wherein if a derived code is stored in all the available storage locations, the memory selector will select one of the memory addresses to be erased and the processor causes the derived code to be stored in that location. 
     
     
       25. A remotely controlled system in accordance with  claim 22 , wherein the processor is prevented from producing the operate output until the processor determines that the derived code corresponds with the stored code a preset plurality of times. 
     
     
       26. A remotely controlled system in accordance with  claim 22 , wherein the processor is prevented from storing a derived code until the same derived code is received a preset plurality of times. 
     
     
       27. A remotely controlled system in accordance with  claim 22  wherein the processor comprises a microprocessor. 
     
     
       28. A remotely controlled system comprising: a plurality of RF transmitters, each of said RF transmitters having its own different, non- user changeable transmitter code and having a transmitter for transmitting when energized, an RF signal carrying a code from which the transmitter code can be derived; a receiver for receiving said coded RF transmissions; a decoder for deriving a code corresponding to the transmitter code of the energized transmitter; a processor for providing in its operate mode an operate output; a mode selector connected to said processor for placing said processor in its program mode; an addressable memory having a plurality of addresses controlled by said processor for storing a plurality of derived codes; a software controlled memory selector controlled by said processor for identifying respective ones of the memory addresses; said software controlled memory selector identifying one of the memory addresses so that the processor, when in its program mode, causes the derived code of one of the transmitters to be stored in said addressable memory at the one memory address, and said software controlled memory selector identifying another memory address so that the processor, when in its program mode, causes the code of a second transmitter to be stored in said addressable memory at the memory address; said processor, when in its operate mode, determining whether the derived code corresponds with at least one of the stored codes and when there is correspondence said processor providing an operate output.   
     
     
       29. A remotely controlled system according to  claim 28  wherein the processor comprises a microprocessor. 
     
     
       30. A remotely controlled system for providing an operate output responsive to transmitted codes comprising: a radio receiver, a decoder connected to receive an output of said radio receiver, a processor connected to receive an output of said decoder and provide the operate output, a selector for selecting a program state connected to said processor to place said processor in the program mode, a memory for storing a plurality of codes connected to said processor when said selector is in the program state position, a memory selector for selecting respective storage addresses in the memory, a plurality of radio transmitters with different non-user changeable codes, said memory selector being adapted to select a first storage location at a time when a first one of said radio transmitters is energized so that the code of said first transmitter will be stored in said memory in the first location and said memory selector being adapted to select a second storage location at a time when a second one of said radio transmitters is energized so that the code of said second transmitter will be stored in said memory in said second location, and said processor placed in the operate mode when said selector is in the operate state so that either of said first and second radio transmitters, when energized cause said processor to provide the operate output. 
     
     
       31. A remotely controlled system according to  claim 30  wherein the processor comprises a microprocessor. 
     
     
       32. A remotely controlled system according to  claim 31  wherein the memory selector comprises a software controlled code location pointer identifying a memory address. 
     
     
       33. A remotely controlled system according to  claim 31  wherein said first and second radio transmitters when energized radiate coded signals and said microprocessor receives and compares coded signals from said first and second transmitters with coded signals stored in said memory and said microprocessor provides the operate output if the received transmitted signal and any one of said coded signals stored in said memory match. 
     
     
       34. A remotely controlled system according to  claim 30  wherein said memory selector has “n” states where “n” is an integer and the codes of “n” transmitters can be stored in said memory when said selector is in the program state. 
     
     
       35. A remotely controlled system according to  claim 30  wherein the code stored in said memory can be changed by placing said selector in the program state and one of said plurality of transmitters is energized which has a code which differs from the code previously stored in said memory. 
     
     
       36. A remotely controlled system according to  claim 32  wherein the microprocessor increments the code location pointer to select the memory addresses to store the respective transmitter codes. 
     
     
       37. A system for controlling the operation of equipment comprising: 
       at least one radio frequency transmitter having a non-user changeable code for transmitting a radio frequency transmission corresponding to the transmitter; 
       a radio frequency receiver being adapted to receive the first-mentioned radio frequency transmission from the first-mentioned radio frequency transmitter and being adapted to receive a second radio frequency transmission from a second radio frequency transmitter having a second non-user changeable code, different from said first non-user changeable code; 
       a program mode designator for designating a program mode; 
       a memory comprising a plurality of storage locations; 
       a processor having a processor controlled code location pointer and being responsive to a program mode designation by said program mode designator and the reception by said radio frequency receiver of said first-mentioned radio frequency transmission for storing a first stored code corresponding to the first-mentioned radio frequency transmitter in one of said plurality of storage locations derived from the processor controlled code location pointer, the processor responsive to said program mode designation by said program mode designator and the reception by said receiver of said second radio frequency transmission for storing a second stored code corresponding to the second radio frequency transmitter in a storage location derived from the processor controlled code location pointer and where the first stored code is not stored, and the processor responsive to an operate mode and the reception of said first-mentioned radio frequency transmission after the storage of said first stored code for operating the equipment and responsive to said operate mode and to the reception of said second radio frequency transmission after the storage of said first and said second stored codes for operating the equipment. 
     
     
       38. A system for controlling the operation of equipment according to  claim 37  wherein said processor controlled code location pointer comprises a software controlled code location pointer. 
     
     
       39. A system for controlling the operation of equipment comprising: 
       a first radio frequency transmitter having a first non-user changeable code and for transmitting a first radio frequency transmission corresponding to the first transmitter; 
       a second radio frequency transmitter having a second non-user changeable code, different from said first non-user changeable code and for transmitting a second radio frequency transmission corresponding to the second transmitter; and 
       an operator for controlling the operation of the equipment, said operator comprising: 
       a radio frequency receiver for receiving said first and said second radio frequency transmissions; 
       a program mode designator for designating a program mode; 
       a memory comprising a plurality of storage locations; 
       a processor having a processor controlled code location pointer and being responsive to a program mode designation by said program mode designator and the reception by said radio frequency receiver of said first radio frequency transmission for storing a first stored code corresponding to the code of the first radio frequency transmitter in one of said plurality of storage locations derived from the processor controlled code location pointer, the processor responsive to said program mode designation by said program mode designator and the reception by said receiver of said second radio frequency transmission for storing a second stored code corresponding to the code of the second radio frequency transmitter in a storage location derived from the processor controlled code location pointer and where the first stored code is not stored, and the processor responsive to an operate mode and the reception of said first radio frequency transmission after the storage of said first stored code for controlling the operator and responsive to said operate mode and to the reception of said second radio frequency transmission after the storage of said first and said second stored codes for controlling the operator. 
     
     
       40. A system for controlling the operation of equipment comprising: 
       a first radio frequency transmitter having a first non-user changeable code and for transmitting a first radio frequency transmission corresponding to the first transmitter; 
       a second radio frequency transmitter having a second non-user changeable code, different from said first non-user changeable code and for transmitting a second radio frequency transmission corresponding to the second transmitter; and 
       an operator for controlling the operation of the equipment, said operator comprising: 
       a radio frequency receiver for receiving said first and said second radio frequency transmissions; 
       a program mode designator for designating a program mode; 
       a memory comprising a plurality of storage locations; 
       a processor having a software controlled code location pointer and being responsive to a program mode designation by said program mode designator and the reception by said radio frequency receiver of said first radio frequency transmission for storing a first stored code corresponding to the code of the first radio frequency transmitter in one of said plurality of storage locations derived from the software controlled code location pointer, the processor responsive to said program mode designation by said program mode designator and the reception by said receiver of said radio frequency transmission for storing a second stored code corresponding to the code of the second radio frequency transmitter in a storage location derived from the software controlled code location pointer and where the first stored code is not stored, and the processor responsive to an operate mode and the reception of said first radio frequency transmission after the storage of said first stored code for controlling the equipment and responsive to said operate mode and to the reception of said second radio frequency transmission after the storage of said first and said second stored codes for controlling the equipment. 
     
     
       41. An operator for controlling operation of equipment comprising, a mechanism connected to said equipment to operate it, a radio receiver, a decoder connected to receive an output of said radio receiver, a microprocessor coupled to receive an output of said decoder and coupled to said mechanism to energize it, a device moveable between operate and program positions to place said microprocessor in the program mode, memory means for storing codes in a plurality of addresses coupled to said microprocessor when said device is in the program position, a memory selector for selecting storage addresses in the memory means, a plurality of radio transmitters with different non-user changeable codes, said memory selector selecting a storage address at a time when a first one of said radio transmitters is energized so that a code corresponding to the code of said first transmitter is be stored in said memory means in said first selected address, and said memory selector selecting a storage address at a time when a second one of said radio transmitters is energized and where the first stored code is not stored so that a code corresponding to the code of said second transmitter will be stored in said memory means at that selected address, and said microprocessor being placed in the operate mode when said device is in the operate position so that either of said first and second radio transmitters when energized cause said microprocessor to energize said mechanism. 
     
     
       42. An operator according to  claim 41  wherein said first and second radio transmitters when energized radiate coded signals, said microprocessor receives and compares coded signals from said first and second transmitters with coded signals stored in said memory means, and said microprocessor produces a controller operate signal if the received transmitted signal and any one of said coded signals stored in said memory means correspond. 
     
     
       43. An operator according to  claim 41  wherein said memory selector has “n” positions where “n” is an integer and the codes corresponding to the codes of “n” transmitters can be stored in said memory means when said device is in the program mode. 
     
     
       44. An operator according to  claim 41  wherein the code corresponding to the code of a transmitter is only stored in said memory means by placing said microprocessor in the program mode, and one of said plurality of transmitters is energized which has a code which differs from the code of a transmitter previously stored in said memory means. 
     
     
       45. An operator according to  claim 41  wherein the memory selector comprises a software controlled code location pointer identifying a memory address. 
     
     
       46. An operator for controlling operation of equipment comprising: a radio receiver, a decoder connected to receive the output of said radio receiver, a microprocessor connected to receive the output of said decoder and coupled to said equipment to energize it, a device coupled to said microprocessor to place said microprocessor in an operate mode or a program mode, memory means for storing a plurality of addresses coupled to said microprocessor when said microprocessor is in the program mode, memory selection means for selecting a storage address in the memory, a plurality of radio transmitters with different non-user changeable codes, said memory selection means being adapted to select a first storage location at a time when a first one of said radio transmitters is energized so that a code corresponding to the code of said first transmitter will be stored in said memory means in the first location, and said memory selection means being adapted to select a storage location when a second one of said radio transmitters is energized, and where the corresponding code of said one transmitter is not stored so that the code corresponding to the code of said second transmitter will be stored in said memory means in that location, and when said microprocessor is placed in the operate mode either of said first and second radio transmitters, when energized cause said microprocessor to energize said equipment. 
     
     
       47. An operator according to  claim 46  wherein the memory selection means comprises a software controlled code location pointer identifying a memory address. 
     
     
       48. An operator according to  claim 46  wherein said first and second radio transmitters when energized radiate coded signals corresponding to the codes in said transmitters, said microprocessor receives and compares coded signals from said first and second transmitters with the coded signals stored in said memory means, and said microprocessor produces an operate signal if the codes in the received transmitted signal and any one of said coded signals stored in said memory means correspond. 
     
     
       49. An operator according to  claim 47  wherein said memory selection means has “n” states where “n” is an integer, and the codes corresponding to the codes of “n” transmitters can be stored in said memory means when said microprocessor is in the program mode. 
     
     
       50. An operator according to  claim 47  wherein the code corresponding to the code of a transmitter is only stored in said memory means by placing said microprocessor in the program mode, and one of said plurality of transmitters is energized which has a code which differs from the code of a transmitter previously stored in said memory means. 
     
     
       51. An operator according to  claim 47  wherein the microprocessor increments the code location pointer to select the memory addresses to store the respective transmitter codes. 
     
     
       52. A system for controlling access to an area comprising: a plurality of RF transmitters, each of said transmitters having its own different non-user changeable transmitter code and having means for transmitting when energized an RF signal carrying a code from which the transmitter code can be derived; a receiver for receiving said coded RF transmissions; a decoder for deriving a code corresponding to the transmitter code in the energized transmitter; processor means for providing in its operate mode an operating signal to grant access to said area and for providing in its program mode a derived code for storage; a device moveable between an operate position and a program position for respectively placing said processor means in its operate mode and program mode; memory means having a plurality of addresses for storing a plurality of codes corresponding to the derived codes under the control of said processor means; a memory address selector controlled by said processor means to identify memory addresses; said memory selector identifying one of the memory addresses so that the processor means, when in its program mode, causes a code corresponding to the derived code of one of the transmitters to be stored in said memory means at the one memory address, and said memory selector identifying a memory address where the corresponding code of the one transmitter is not stored so that the processor means, when in its program mode, causes a code corresponding to the derived code of a second transmitter to be stored in said memory means at that identified memory address; said processor means, when in its operate mode, determining whether the derived code and one of the stored codes correspond, said processor means providing an operating signal to grant access to the area upon correspondence. 
     
     
       53. A system in accordance with  claim 52 , wherein the processor means determines whether the corresponding derived code has been previously stored in any of the memory addresses and if the corresponding derived code is already stored, the processor means does not cause the corresponding derived code to be stored. 
     
     
       54. A system in accordance with  claim 52 , wherein corresponding derived codes have been stored in all the available storage addresses, the memory selector will select one of such already written storage addresses and the processor means causes the most recently received corresponding derived code to be stored in that address. 
     
     
       55. A system in accordance with  claim 52 , wherein means are provided to prevent the processor means from granting access until the processor means determines that the derived code corresponds with the stored code a preset plurality of times. 
     
     
       56. A system in accordance with  claim 52 , wherein means are provided to prevent the processor means from storing a corresponding derived code until the same derived code is received a preset plurality of times. 
     
     
       57. A system for granting access to an area comprising: a plurality of RF transmitters, each of said RF transmitters having its own different, non-user changeable transmitter code and having a transmitter for transmitting when energized, an RF signal carrying a code from which the transmitter code can be derived; a receiver for receiving said coded RF transmissions; a decoder for deriving a code corresponding to the transmitter code of the energized transmitter; a processor for providing in its operate mode an operating signal to a mechanism to energize it; a mode selector for placing said processor in its program mode; an addressable memory having a plurality of addresses for storing a plurality of derived codes; a software controlled memory selector controlled by said processor for identifying respective ones of the memory addresses; said software controlled memory selector identifying one of the memory addresses so that the processor, when in its program mode, causes a code corresponding to the derived code of one of the transmitters to be stored in said addressable memory at the one memory address, and said software controlled memory selector identifying another memory address so that the processor, when in its program mode, causes the derived code of a second transmitter to be stored in said addressable memory at the other memory address; said processor, when in its operate mode, determining whether the derived code corresponds with at least one of the stored derived codes and when there is correspondence said processor providing an operating signal to grant access to the area. 
     
     
       58. A system according to  claim 37  wherein the processor comprises a microprocessor. 
     
     
       59. A system according to  claim 39  wherein the processor comprises a microprocessor. 
     
     
       60. A system according to  claim 40  wherein the processor comprises a microprocessor. 
     
     
       61. A system according to  claim 52  wherein said processor means comprises a microprocessor. 
     
     
       62. A system according to  claim 57  wherein the processor comprises a microprocessor.