Semiconductor integrated logic circuit device using a pass transistor

Abstract

The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal is connected to a plurality of input terminals through source-drain paths of active devices connected in the tree form, and gate electrodes of the active devices are connected to other input terminals. Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc., and for reducing the cost of production.

What is claimed is:  
     
       1. A semiconductor integrated circuit device including a plurality of cells, at least one of said cells comprising first, second, third and fourth active devices, first and second nodes, first, second, third, fourth, fifth, sixth and seventh input terminals, and an output terminal, wherein: 
       said first active device has a first gate coupled to said first input terminal;  
       said second active device has a second gate coupled to said second input terminal;  
       said third active device has a third gate coupled to said third input terminal;  
       said fourth active device has a fourth gate coupled to said fourth input terminal;  
       said first active device has a first source-drain path coupled between said second node and said seventh input terminal;  
       said second active device has a second source-drain path coupled between said second node and said sixth input terminal;  
       said third active device has a third source-drain path coupled between said first node and said second node;  
       said fourth active device has a fourth source-drain path coupled between said first node and said fifth input terminal;  
       said first node is coupled to said output terminal;  
       said cell has a first diffusion layer region and a second diffusion layer region;  
       first and second electrodes traverse said first diffusion layer region to define a first area of said first diffusion layer region sandwiched by said first and second electrodes, and second and third areas of said first diffusion layer region not sandwiched by said first and second electrodes;  
       third and fourth electrodes traverse said second diffusion layer region to define a fourth area of said second diffusion layer region sandwiched by said third and fourth electrodes, and fifth and sixth areas of said second diffusion layer region not sandwiched by said third and fourth electrodes;  
       said first node is coupled to said first area;  
       said second node is coupled to said second and fourth areas;  
       said first input terminal is coupled to said fourth electrode;  
       said second input terminal is coupled to said third electrode;  
       said third input terminal is coupled to said second electrode;  
       said fourth input terminal is coupled to said first electrode;  
       said fifth input terminal is coupled to said third area;  
       said sixth input terminal is coupled to said fifth area; and,  
       said seventh input terminal is coupled to said sixth area.  
     
     
       2. The semiconductor integrated circuit device according to  claim 1 , wherein said first and second diffusion layer regions are disposed between a first power supply wiring conductor for supplying a first electric potential and a second power supply wiring conductor for supplying a second electric potential. 
     
     
       3. The semiconductor integrated circuit device according to  claim 2 , wherein said first and second power supply wiring conductors are substantially parallel to each other, and said first to sixth areas are juxtaposed in a direction of extension of said first and second power supply wiring conductors. 
     
     
       4. The semiconductor integrated circuit device according to  claim 3 , wherein said first to seventh input terminals are aligned between said first or second power supply wiring conductor and said first and second diffusion layer regions. 
     
     
       5. A semiconductor integrated circuit device including a plurality of cells, at least one of said cells comprising first, second, third and fourth active devices, first and second nodes, first, second, third, fourth, fifth, sixth and seventh input terminals, and an output terminal, wherein: 
       said first active device has a first gate coupled to said first input terminal for receiving a first signal;  
       said second active device has a second gate coupled to said second input terminal for receiving a second signal having an opposite phase to the first signal;  
       said third active device has a third gate coupled to said third input terminal;  
       said fourth active device has a fourth gate coupled to said fourth input terminal;  
       said first active device has a first source-drain path coupled between said second node and said seventh input terminal;  
       said second active device has a second source-drain path coupled between said second node and said sixth input terminal;  
       said third active device has a third source-drain path coupled between said first node and said second node;  
       said fourth active device has a fourth source-drain path coupled between said first node and said fifth input terminal;  
       said first node is coupled to said output terminal;  
       said cell has a first diffusion layer region and a second diffusion layer region;  
       first and second electrodes traverse said first diffusion layer region to define a first area of said first diffusion layer region sandwiched by said first and second electrodes, and second and third areas of said first diffusion layer region not sandwiched by said first and second electrodes;  
       third and fourth electrodes traverse said second diffusion layer region to define a fourth area of said second diffusion layer region sandwiched by said third and fourth electrodes, and fifth and sixth areas of said second diffusion layer region not sandwiched by said third and fourth electrodes;  
       said first node is coupled to said first area;  
       said second node is coupled to said second and fourth areas;  
       said first input terminal is coupled to said fourth electrode;  
       said second input terminal is coupled to said third electrode;  
       said third input terminal is coupled to said second electrode;  
       said fourth input terminal is coupled to said first electrode;  
       said fifth input terminal is coupled to said third area;  
       said sixth input terminal is coupled to said fifth area; and, said seventh input terminal is coupled to said sixth area.  
     
     
       6. The semiconductor integrated circuit device according to  claim 5 , wherein said first and second diffusion layer regions are disposed between a first power supply wiring conductor for supplying a first electric potential and a second power supply wiring conductor for supplying a second electric potential. 
     
     
       7. The semiconductor integrated circuit device according to  claim 6 , wherein said first and second power supply wiring conductors are substantially parallel to each other, and said first to sixth areas are juxtaposed in a direction of extension of said first and second power supply wiring conductors. 
     
     
       8. The semiconductor integrated circuit device according to  claim 7 , wherein said first to seventh input terminals are aligned between said first or second power supply wiring conductor and said first and second diffusion layer regions. 
     
     
       9. A semiconductor integrated circuit device including a plurality of cells, at least one of said cells comprising first, second, third and fourth active devices, first and second nodes, first, second, third, fourth, fifth, sixth and seventh points, and an output terminal, wherein: 
       said first active device has a first gate coupled to said first point for receiving a first signal;  
       said second active device has a second gate coupled to said second point for receiving a second signal having an opposite phase to the first signal;  
       said third active device has a third gate coupled to said third point;  
       said fourth active device has a fourth gate coupled to said fourth point;  
       said first active device has a first source-drain path coupled between said second node and said seventh point;  
       said second active device has a second source-drain path coupled between said second node and said sixth point;  
       said third active device has a third source-drain path coupled between said first node and said second node;  
       said fourth active device has a fourth source-drain path coupled between said first node and said fifth point;  
       said first node is coupled to said output terminal;  
       said cell has a first diffusion layer region and a second diffusion layer region;  
       first and second electrodes traverse said first diffusion layer region to define a first area of said first diffusion layer region sandwiched by said first and second electrodes, and second and third areas of said first diffusion layer region not sandwiched by said first and second electrodes;  
       third and fourth electrodes traverse said second diffusion layer region to define a fourth area of said second diffusion layer region sandwiched by said third and fourth electrodes, and fifth and sixth areas of said second diffusion layer region not sandwiched by said third and fourth electrodes;  
       said first node is coupled to said first area;  
       said second node is coupled to said second and fourth areas;  
       said first point is coupled to said fourth electrode;  
       said second point is coupled to said third electrode;  
       said third point is coupled to said second electrode;  
       said fourth point is coupled to said first electrode;  
       said fifth point is coupled to said third area;  
       said sixth point is coupled to said fifth area; and  
       said seventh point is coupled to said sixth area; and  
       at least a part of said first and second diffusion layer regions are disposed between a first power supply wiring conductor for supplying a first electric potential and a second power supply wiring conductor for supplying a second electric potential.  
     
     
       10. A design method for designing a semiconductor integrated circuit including a first logic circuit and a second logic circuit, wherein a basic logic function of said first logic circuit is different from a basic logic function of said second logic circuit, comprising: 
       
         calling a cell data from a cell library stored in a memory unit of a computer for computer aided design, said cell library storing a plurality of cell data each of which includes a predetermined design rule of a plurality of circuit elements, wherein said predetermined design rule includes information of at least connections between one and at least another of said circuit elements and dispositions of said circuit elements;  
       
       
         designating a first signal application form to said called cell data based on said basic logic function of said first logic circuit to design said first logic circuit; and  
       
       
         designating a second signal application form to said called cell data based on said basic logic function of said second logic circuit to design said second logic circuit;  
       
       
         wherein in both of said first logic circuit and said second logic circuit, said plurality of said circuit elements is disposed and is interconnected to at least another of said circuit elements in a same way in accordance with said predetermined design rule, and  
       
       
         wherein said circuit elements include first, second, third and fourth active devices, first, second, third, fourth, fifth, sixth and seventh input terminals and an output terminal, wherein,  
       
       
         said first active device has a first control electrode coupled to said first input terminal inputted a first signal;  
       
       
         said second active device has a second control electrode coupled to said second input terminal inputting a second signal;  
       
       
         said third active device has a third control electrode coupled to said third input terminal inputting a third signal;  
       
       
         said fourth active device has a fourth control electrode coupled to said fourth input terminal inputting a fourth signal;  
       
       
         said first active device has a first current path coupled between a second node and said seventh input terminal;  
       
       
         said second active device has a second current path coupled between said second node and a sixth input terminal;  
       
       
         said third active device has a third current path coupled between a first node and said second node;  
       
       
         said fourth active device has a fourth current path coupled between said first node and said fifth input terminal; and  
       
       
         said first node is coupled to said output terminal.  
       
     
     
       11. A design method according to  claim 10 , 
       
         wherein said predetermined design rule of said plurality of said circuit elements includes information of positions of input/output terminals.  
       
     
     
       12. A design method according to  claim 10 , further comprising: 
         designating positions of said first and second logic circuits within said semiconductor integrated circuit and external - wirings of said first and second logic circuits within said semiconductor integrated circuit.    
     
     
       13. A design method according to  claim 10 , 
       
         wherein said first and second control electrodes traverse a first impurity region to define a first area of said first impurity region sandwiched by said first and second control electrodes, and second and third areas of said first impurity region not sandwiched by said first and second control electrodes;  
       
       
         said third and fourth control electrodes traverse a second impurity region to define a fourth area of said second impurity region sandwiched by said third and fourth control electrodes, and fifth and sixth areas of said second impurity region not sandwiched by said third and fourth control electrodes;  
       
       
         said first node is coupled to said first area;  
       
       
         said second node is coupled to said second and fourth areas;  
       
       
         said fifth input terminal is coupled to said third area;  
       
       
         said sixth input terminal is coupled to said fifth area; and  
       
       
         said seventh input terminal is coupled to said sixth area.  
       
     
     
       14. A design method according to  claim 10 , 
       
         wherein said first and second signals are complementary signals and third and fourth signals are complementary signals.  
       
     
     
       15. A design method according to  claim 10 , 
       
         wherein said first node is coupled to said output terminal via an inverter circuit.  
       
     
     
       16. A design method for designing a semiconductor integrated circuit including a first logic circuit and a second logic circuit, wherein a basic logic function of said first logic circuit is different from a basic logic function of said second logic circuit, comprising: 
       
         calling a cell data from a cell library stored in a memory unit of a computer for computer aided design, said cell library storing a plurality of cell data each of which includes a predetermined design rule of a plurality of circuit elements, wherein said predetermined design rule includes information of at least connections between one and at least another of said circuit elements and dispositions of said circuit elements;  
       
       
         designating a first signal application form to said called cell data based on said basic logic function of said first logic circuit to design said first logic circuit; and  
       
       
         designating a second signal application form to said called cell data based on said basic logic function of said second logic circuit to design said second logic circuit;  
       
       
         wherein in both of said first logic circuit and said second logic circuit, said plurality of said circuit elements is disposed and is interconnected to at least another of said circuit elements in a same way in accordance with said predetermined design rule, and  
       
       
         wherein said circuit elements includes first, second, third and fourth active devices, first and second inverter circuits, first, second, third, fourth and fifth input terminals and an output terminal wherein,  
       
       
         said first active device has a first control electrode coupled to said first input terminal;  
       
       
         said second active device has a second control electrode coupled to said first input terminal via said first inverter circuit;;  
       
       
         said third active device has a third control electrode coupled to said third input terminal;  
       
       
         said fourth active device has a fourth control electrode coupled to said second input terminal via said second inverter circuit;  
       
       
         said first active device has a first current path coupled between a second node and said fifth input terminal;  
       
       
         said second active device has a second current path coupled between said second node and said fourth input terminal;  
       
       
         said third active device has a third current path coupled between a first node and said second node;  
       
       
         said fourth active device has a fourth current path coupled between said first node and said third input terminal;  
       
       
         said first node is coupled to said output terminal.  
       
     
     
       17. A design method according to  claim 16 , 
       
         wherein said first and second control electrodes traverse a first impurity region to define a first area of said first impurity region sandwiched by said first and second control electrodes, and second and third areas of said first impurity region not sandwiched by said first and second control electrodes;  
       
       
         said third and fourth control electrodes traverse a second impurity region to define a fourth area of said second impurity region sandwiched by said third and fourth gate electrodes, and fifth and sixth areas of said second impurity region not sandwiched by said third and fourth control electrodes;  
       
       
         said first node is coupled to said first area;  
       
       
         said second node is coupled to said second and fourth areas;  
       
       
         said third input terminal is coupled to said third area;  
       
       
         said fourth input terminal is coupled to said fifth area; and  
       
       
         said fifth input terminal is coupled to said third area.  
       
     
     
       18. A design method according to  claim 16 , 
       
         wherein said first node is coupled to said output terminal via an inverter circuit.  
       
     
     
       19. A semiconductor integrated circuit comprising: 
       
         a first logic circuit; and  
       
       
         a second logic circuit having a basic logic function different from a basic logic function of said first logic circuit;  
       
       
         wherein each of said first and second logic circuits includes a plurality of circuit elements disposed and interconnected with at least another of said circuit elements in a same way in said first logic circuit and said second logic circuit,  
       
       
         wherein a plurality of first signals according to said basic logic function of said first logic circuit are supplied to input nodes of said first logic circuit,  
       
       
         wherein a plurality of second signals according to said basic logic function of said second logic circuit are supplied to input nodes of said second logic circuit,  
       
       
         wherein a difference of basic logic functions between said first and second logic circuits is accomplished by a difference between a signal application form of said first signals and a signal application form of said second signals, and  
       
       
         wherein said circuit elements includes first, second, third and fourth active devices, first, second, third, fourth, fifth sixth and seventh input nodes and an output node, wherein,  
       
       
         said first active device has a first control electrode coupled to said first input terminal;  
       
       
         said second active device has a second control electrode coupled to said second input node;  
       
       
         said third active device has a third control electrode coupled to said third input node;  
       
       
         said fourth active device has a fourth control electrode coupled to said fourth input terminal node;  
       
       
         said first active device has a first current path coupled between a second node and said seventh input node;  
       
       
         said second active device has a second current path coupled between said second node and a sixth input node;  
       
       
         said third active device has a third current path coupled between a first node and said second node; and  
       
       
         said fourth active device has a fourth current path coupled between said first node and said fifth input node.  
       
     
     
       20. A semiconductor integrated circuit according to  claim 19 : 
       
         wherein each of a plurality of said first signals and said second signals is one of an output signal from another logic circuit, an input signal from external of said semiconductor integrated circuit, and a first operating potential and a second operating potential of said semiconductor integrated circuit.  
       
     
     
       21. A semiconductor integrated circuit according to  claim 19 : 
       
         wherein wirings between said circuit elements of said first logic circuit and said second logic circuit are established by a first layer wiring, and  
       
       
         wherein wirings to said first logic circuit and said second logic circuit for inputting said first and second signals are established by a second or higher layer wirings.  
       
     
     
       22. A semiconductor integrated circuit according to  claim 19 , 
       
         wherein a signal inputted to said first input node and a signal inputted to said second input node are complementary signals and a signal inputted to said third input node and a signal inputted to said fourth input node are complementary signals.  
       
     
     
       23. A semiconductor integrated circuit according to  claim 19 , 
       
         wherein one of said basic logic function of said first logic circuit and said basic logic function of said second logic circuit is one of NAND and NOR, and another of said basic logic function of said first logic circuit and said basic logic function of said second logic circuit is another of NAND and NOR.  
       
     
     
       24. An electric data of a cell for a semiconductor integrated circuit, stored in a memory unit of a computer for computer aided design comprising: 
       
         positioning information data of first, second, third, fourth, fifth, sixth and seventh input terminal and an output terminal included in said cell;  
       
       
         disposing information data of first, second, third and fourth active devices included in said cell; and  
       
       
         connecting information data of said first, second, third and fourth active devices and first and second nodes included in said cell;  
       
       
         wherein said disposing information enables a first control electrode of said first active device and a second control electrode of said second active device to traverse a first impurity region to define a first area of said first impurity region sandwiched by said first and second gate electrodes, and second and third areas of said first impurity region not sandwiched by said first and second gate electrodes;  
       
       
         wherein said disposing information enables a third control electrode of said third active device and a fourth control electrode of said fourth active device to traverse a second impurity region to define a fourth area of said first impurity region sandwiched by said third and fourth gate electrodes, and fifth and fourth areas of said second impurity region not sandwiched by said third and fourth gate electrodes;  
       
       
         wherein said connecting information enables to couple said first control electrode to said first input terminal,  
       
       
         wherein said connecting information enables to couple said second control electrode to said second input terminal,  
       
       
         wherein said connecting information enables to couple said third control electrode to said third input terminal,  
       
       
         wherein said connecting information enables to couple said fourth control electrode to said fourth input terminal,  
       
       
         wherein said connecting information enables to couple a first current path of said first active device between said second node and said seventh input terminal,  
       
       
         wherein said connecting information enables to couple a second current path of said second active device between said second node and said sixth input terminal,  
       
       
         wherein said connecting information enables to couple a third current path of said third active device between said first node and said second node,  
       
       
         wherein said connecting information enables to couple a fourth current path of said fourth active device between said first node and said fifth input terminal,  
       
       
         wherein said connecting information enables to couple said first node to said output terminal,  
       
       
         wherein said connecting information enables to couple said first node to said first area,  
       
       
         wherein said connecting information enables to couple said second node to said second and fourth areas,  
       
       
         wherein said connecting information enables to couple said fifth input terminal to said third area,  
       
       
         wherein said connecting information enables to couple said sixth input terminal to said fifth area, and  
       
       
         wherein said connecting information enables to couple said seventh input terminal to said sixth area.  
       
     
     
       25. An electric data according to  claim 24 , 
       
         wherein said connecting information data enables to designate that a first signal inputted to said first input terminal and a second signal inputted to said second input terminal and complimentary signals, and  
       
       
         wherein said connecting information data enables to designate that a third signal inputted to said third input terminal and a fourth signal inputted to said fourth input terminal are complimentary signals.  
       
     
     
       26. An electric data of a cell for a semiconductor integrated circuit, stored in a memory unit of a computer for computer aided design comprising: 
       
         positioning information data of first, second, third, fourth and fifth input terminals and an output terminal included in said cell;  
       
       
         disposing information data of first, second, third and fourth active devices included in said cell; and  
       
       
         connecting information data of said first, second, third and fourth active devices, first and second nodes and first and second inverter circuits included in said cell;  
       
       
         wherein said disposing information enables a first control electrode of said first active device and a second control electrode of said second active device to traverse a first impurity region to define a first area of said first impurity region sandwiched by said first and second control electrodes, and second and third areas of said first impurity region not sandwiched by said first and second control electrodes;  
       
       
         wherein said disposing information enables a third control electrode of said third active device and a fourth control electrode of said fourth active device to traverse a second impurity region to define a fourth area of said first impurity region sandwiched by said third and fourth control electrodes, and fifth and fourth areas of said second impurity region not sandwiched by said third and fourth control electrodes;  
       
       
         wherein said connecting information enables to couple said first control electrode to said first input terminal,  
       
       
         wherein said connecting information enables to couple said second control electrode to said first input terminal via said first inverter circuit,  
       
       
         wherein said connecting information enables to couple said third control electrode to said second input terminal,  
       
       
         wherein said connecting information enables to couple said fourth control electrode to said second input terminal via said second inverter circuit,  
       
       
         wherein said connecting information enables to couple a first current path of said first active device between said second node and said fifth input terminal,  
       
       
         wherein said connecting information enables to couple a second current path of said second active device between said second node and said fourth input terminal,  
       
       
         wherein said connecting information enables to couple a third current path of said third active device between said first node and said second node,  
       
       
         wherein said connecting information enables to couple a fourth current path of said fourth active device between said first node and said third input terminal,  
       
       
         wherein said connecting information enables to couple said first node to said output terminal,  
       
       
         wherein said connecting information enables to couple said first node to said first area,  
       
       
         wherein said connecting information enables to couple said second node to said second and fourth areas,  
       
       
         wherein said connecting information enables to couple said third input terminal to said third area,  
       
       
         wherein said connecting information enables to couple said fourth input terminal to said fifth area, and  
       
       
         wherein said connecting information enables to couple said fifth input terminal to said sixth area.  
       
     
     
       27. An electric data of a cell for a semiconductor integrated circuit, stored in a memory unit of a computer for computer aided design comprising: 
       
         positioning information data of a plurality of input terminals and an output terminal included in said cell;  
       
       
         disposing information data of a plurality of circuit elements included in said cell; and  
       
       
         connecting information data of said plurality of circuit elements in said cell;  
       
       
         wherein said electric data of said cell enables design in both a first logic circuit and a second logic circuit, and said circuit elements are enabled to be disposed and are enabled to be connected with at least one of said circuit elements in a same way in said first logic circuit and said second logic circuit,  
       
       
         wherein a combination of said electric data and information of signal application forms makes difference of a basic logic function between said first logic circuit and said second logic circuit, said information of signal application forms enables to designate a plurality of first signals inputted to said first logic circuit and a plurality of second signals inputted to said second logic circuit;  
       
       
         wherein a difference of signal application forms between said first signals and said second signals enables to accomplish a difference of said basic logic function between said first logic circuit and said second logic circuit,  
       
       
         wherein said connecting information enables to couple a first control electrode of a first active device to a first input node,  
       
       
         wherein said connecting information enables to couple a second control electrode of a second active device to a second input node;  
       
       
         wherein said connecting information enables to couple a third control electrode of a third active device to a third input node;  
       
       
         wherein said connecting information enables to couple a fourth control electrode of a fourth active device to a fourth input node;  
       
       
         wherein said connecting information enables to couple a first current path of said first active device between a second node and a seventh input node;  
       
       
         wherein said connecting information enables to couple a second current path of said second active device between said second node and a sixth input node;  
       
       
         wherein said connecting information enables to couple a third current path of said third active device between said first node and said second node;  
       
       
         wherein said connecting information enables to couple a fourth current path of said fourth active device between said first node and said fifth input node.  
       
     
     
       28. An electric data according to  claim 27 , 
       
         wherein one of said basic logic function of said first logic circuit and said basic logic function of said second logic circuit is one of NAND and NOR, and another of said basic logic function of said first logic circuit and said basic logic function of said second logic circuit is another of NAND and NOR.  
       
     
     
       29. A semiconductor integrated circuit device including a plurality of cells, at least one of said cells comprising first, second, third and fourth active devices, first and second nodes, first, second, third, fourth, fifth, sixth and seventh input nodes, wherein: 
       
         said first active device has a first control electrode coupled to said first input node;  
       
       
         said second active device has a second control electrode coupled to said second input node;  
       
       
         said third active device has a third control electrode coupled to said third input node;  
       
       
         said fourth active device has a fourth control electrode coupled to said fourth input node;  
       
       
         said first active device has a first current path coupled between a second node and said seventh input node;  
       
       
         said second active device has a second current path coupled between said second node and a sixth input node;  
       
       
         said third active device has a third current path coupled between a first node and said second node;  
       
       
         said fourth active device has a fourth current path coupled between said first node and said fifth input node;  
       
       
         said first and second control electrodes traverse a first impurity region to define a first area of said first impurity region sandwiched by said first and second control electrodes, and second and third areas of said first impurity region not sandwiched by said first and second control electrodes;  
       
       
         said third and fourth control electrodes traverse a second impurity region to define a fourth area of said second impurity region sandwiched by said third and fourth control electrodes, and fifth and sixth areas of said second impurity region not sandwiched by said third and fourth control electrodes;  
       
       
         said first node is coupled to said first area;  
       
       
         said second node is coupled to said second and fourth areas;  
       
       
         said fifth input node is coupled to said third area;  
       
       
         said sixth input node is coupled to said fifth area; and  
       
       
         said seventh input node is coupled to said sixth area.  
       
     
     
       30. A semiconductor integrated circuit device according to  claim 29 , 
       
         wherein a signal inputted to said first input node and a signal inputted to said second input node are complementary signals and a signal inputted to said third input node and a signal inputted to said fourth input node are complementary signals.  
       
     
     
       31. An semiconductor integrated circuit device according to  claim 29 , 
       
         wherein said cells include first and second inverter circuits;  
       
       
         said first inverter circuit is disposed between said first input node and said second input node; and  
       
       
         said second inverter circuit is disposed between said third input node and said fourth input node.  
       
     
     
       32. A semiconductor integrated circuit device according to  claim 29 , 
       
         wherein said first and second impurity regions are disposed between a first power supply wiring conductor for supplying a first electric potential and a second power supply wiring conductor for supplying a second electric potential.  
       
     
     
       33. A semiconductor integrated circuit device according to  claim 32 , 
       
         wherein said first and second power supply wiring conductors are substantially parallel to each other, and said first to sixth areas are juxtaposed in a direction of extension of said first and second power supply wiring conductors.