Method and circuit for detecting a fault in a clock signal for microprocessor electronic devices including memory elements

Abstract

An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor. The circuit monitors the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.

We claim:  
     
       1. A non-volatile electrically programmable and erasable memory device including a memory cell matrix and a microprocessor interlocked with a circuit generating at least one oscillating periodic clock signal, comprising: 
       a circuit for generation of a reset signal for said microprocessor having an input terminal coupled with an output of the circuit generating at least one oscillating clock signal and an output terminal coupled with a reset input of the microprocessor;  
       wherein said circuit for generating of a reset signal detects a stop in the oscillation of said clock signal and generates the reset signal in response to detecting the stop in the oscillation of said clock signal.  
     
     
       2. The memory device of  claim 1  wherein said circuit for generation of a reset signal is  detects the stop in said clock signal both at a high logic level and a low logic level. 
     
     
       3. The memory device of  claim 2  wherein the circuit includes an output terminal and wherein the output terminal of said circuit for generation of a reset signal is connected to a first input of a logic gate having an output connected to the reset input of the microprocessor. 
     
     
       4. The memory device of  claim 3  wherein said logic gate is an AND type logic gate having at least two input terminals and one output terminal. 
     
     
       5. A non-volatile electrically programmable and erasable memory device including a memory cell matrix and a microprocessor interlocked with a circuit generating at least one oscillating periodic clock signal, comprising: 
       
         a circuit for generation of a reset signal for said microprocessor having an input terminal coupled with an output of the circuit generating at least one oscillating clock signal and an output terminal coupled with a reset input of the microprocessor;  
       
       
         wherein said circuit for generation of a reset signal detects a stop in the oscillation of said clock signal; 
       
       The memory device of  claim 1  wherein said circuit for generation of a reset signal comprises:  comprising, 
       a first input stage incorporating a first complementary pair of transistors connected between a positive pole of a supply voltage generator and a negative pole of said supply voltage generator, control terminals of the first complementary pair of transistors being both connected to said input terminal and an intermediate circuit node between the transistors of the first complementary pair of transistors being connected to a first input of a logic gate having an output terminal connected to the output terminal of the circuit for generation of a reset signal; , 
       a first capacitive element connected between the intermediate circuit node between the transistors of the first complimentary pari of transistors and a first reference potential; , 
       a second input stage comprising a second complimentary pair of transistors connected between the positive pole and the negative pole of said supply voltage generator, control terminals of the second complimentary pair of transistors being both connected to said input terminal through an inverting gate and an intermediate circuit node between the transistors of the second complimentary pair of transistors being connected to a second input of said logic gate;  , and  
       a second capacitive element connected between the intermediate circuit node between the transistors of the second complimentary pair of transistors and a second terminal connected to a second reference potential.  
     
     
       6. The memory device of  claim 5  wherein each of said first and second complimentary pairs of transistors is made up of an n-channel MOS transistor and a p-channel MOS transistor. 
     
     
       7. The memory device of  claim 6  wherein the p-channel MOS transistors of said first and second complimentary pairs of transistors have conduction resistances lower than the conduction resistances of the n-channel MOS transistors. 
     
     
       8. The memory device of  claim 5  wherein said logic gate is an AND type logic gate having at least two input terminals and one output terminal. 
     
     
       9. The memory device of  claim 5  wherein said first reference potential coincides with said second reference potential. 
     
     
       10. The memory device of  claim 5  wherein the intermediate circuit node between the transistors of the first complimentary pair of transistors is connected through a first junction element to said positive pole of the supply voltage generator and the intermediate circuit node between the transistors of the second complimentary pair of transistors is connected through a second junction element to said positive pole of the supply voltage generator. 
     
     
       11. The memory device of  claim 10  wherein said first and second junction elements are each provided by means of a p-channel MOS transistor. 
     
     
       12. A clock detector, comprising: 
       
         a detector input terminal operable to receive a clock signal;  
       
       
         a detector output terminal; and  
       
       
         a circuit coupled to the detector input and output terminals and operable to generate a first signal on the detector output terminal if the clock signal has a first predetermined characteristic and operable to generate a second signal on the detector output terminal if the clock signal has a second predetermined characteristic, the circuit comprising,  
       
       
         a first stage operable to generate a third signal in response to the clock signal,  
       
       
         a second stage operable to generate a fourth signal in response to the clock signal, and  
       
       
         a third stage coupled to the first and second stages and operable to generate the first signal if the third and fourth signals are equal and operable to generate the second signal if the third and fourth signals are unequal. 
       
     
     
       13. The clock detector of  claim 12  wherein the circuit is operable to: 
       
         generate the first signal if the clock signal has a nonzero frequency; and  
       
       
         generate the second signal if the clock signal has a zero frequency. 
       
     
     
       14. A clock detector, comprising: 
       
         a detector input terminal operable to receive a clock signal;  
       
       
         a detector output terminal; and  
       
       
         a circuit coupled to the detector input and output terminals and operable to generate a first signal on the detector output terminal if the clock signal has a first predetermined characteristic and operable to generate a second signal on the detector output terminal if the clock signal has a second predetermined characteristic, the circuit comprising,  
       
       
         a first inverter operable to generate a third signal in response to the clock signal,  
       
       
         a second inverter operable to generate a fourth signal in response to the clock signal, and  
       
       
         a logic gate coupled to the first and second stages and operable to generate the first signal if the third and fourth signals are equal and operable to generate the second signal if the third and fourth signals are unequal. 
       
     
     
       15. A clock detector, comprising: 
       
         a detector input terminal operable to receive a clock signal;  
       
       
         a detector output terminal; and  
       
       
         a circuit coupled to the detector input and output terminals and operable to generate a first signal on the detector output terminal if the clock signal has a first predetermined characteristic and operable to generate a second signal on the detector output terminal if the clock signal has a second predetermined characteristic, the circuit comprising,  
       
       
         a first inverter having an input terminal coupled to the detector input terminal and having an output terminal,  
       
       
         a first capacitor coupled to the output terminal of the first inverter,  
       
       
         a second inverter having an input terminal coupled to the detector input terminal and having an output terminal,  
       
       
         a second capacitor coupled to the output terminal of the second inverter, and  
       
       
         a logic gate having first and second input terminals respectively coupled to the output terminals of the first and second inverters and having an output terminal coupled to the detector output terminal. 
       
     
     
       16. A clock detector, comprising: 
       
         a detector input terminal operable to receive a clock signal;  
       
       
         a detector output terminal; and  
       
       
         a circuit coupled to the detector input and output terminals and operable to generate a first signal on the detector output terminal if the clock signal has a first predetermined characteristic and operable to generate a second signal on the detector output terminal if the clock signal has a second predetermined characteristic, the circuit comprising,  
       
       
         a first inverter having an input terminal and an output terminal,  
       
       
         a first capacitor coupled to the output terminal of the first inverter,  
       
       
         a second inverter having an input terminal coupled to the detector input terminal and having an output terminal,  
       
       
         a second capacitor coupled to the output terminal of the second inverter,  
       
       
         a third inverter having an input terminal coupled to the detector input terminal and having an output terminal coupled to the input terminal of the first inverter, and  
       
       
         a logic gate having first and second input terminals respectively coupled to the output terminals of the first and second inverters and having an output terminal coupled to the detector output terminal. 
       
     
     
       17. A circuit comprising: 
       
         a functional circuit operable to receive a clock signal and a supply signal; and  
       
       
         a control circuit coupled to the functional circuit and operable to receive the clock and supply signals, to allow the functional circuit to operate if the clock signal has a first predetermined characteristic and the supply signal has a first predetermined relationship to a predetermined threshold, and to reset the functional circuit if the clock signal has a second predetermined characteristic or if the supply signal has a second predetermined relationship to the predetermined threshold. 
       
     
     
       18. The circuit of  claim 17  wherein the functional circuit comprises a processor. 
     
     
       19. The circuit of  claim 17  wherein: 
       
         the control circuit is operable to allow the functional circuit to operate if the clock signal is transitioning between first and second signal levels and the supply signal is greater than the predetermined threshold; and  
       
       
         the control circuit is operable to reset the functional circuit if the clock signal is at a constant signal level or if the supply signal is less than the predetermined threshold. 
       
     
     
       20. A circuit, comprising: 
       
         a functional circuit operable to receive a clock signal, a supply signal, and a reset signal;  
       
       
         a reset circuit coupled to the functional circuit and operable to generate the reset signal; and  
       
       
         a control circuit coupled to the reset circuit and operable to receive the clock signal and the supply signal, the control signal operable to cause the reset circuit to generate the reset signal if the clock signal has a predetermined characteristic or if the supply signal has a predetermined relationship to a predetermined threshold. 
       
     
     
       21. The circuit of  claim 20  wherein the functional circuit comprises a processor. 
     
     
       22. The circuit of  claim 20 , further comprising: 
       
         a memory circuit coupled to the functional circuit; and  
       
       
         wherein the functional circuit comprises a processor. 
       
     
     
       23. The circuit of  claim 20 , further comprising: 
       
         a nonvolatile memory circuit coupled to the functional circuit; and  
       
       
         wherein the functional circuit comprises a processor. 
       
     
     
       24. The circuit of  claim 20  wherein the reset circuit comprises a logic gate having an input terminal coupled to the control circuit and having an output terminal coupled to the functional circuit. 
     
     
       25. The circuit of  claim 20  wherein the control circuit is operable to cause the reset circuit to generate the reset signal if the clock signal is at a constant signal level or if the supply signal is less than the predetermined threshold. 
     
     
       26. A circuit comprising: 
       
         a memory circuit operable to store data;  
       
       
         a reset circuit operable to generate a reset signal;  
       
       
         a control circuit coupled to the reset circuit, operable to receive a clock signal, and operable to cause the reset circuit to generate the reset signal if the clock signal has a predetermined characteristic; and  
       
       
         a processor coupled to the memory circuit and to the reset circuit, the processor operable to receive the clock signal and, in response to the reset signal, being unable to alter the data stored in the memory circuit. 
       
     
     
       27. The circuit of  claim 26  wherein the memory circuit comprises a nonvolatile memory circuit. 
     
     
       28. The circuit of  claim 26  wherein the control circuit is operable to cause the reset circuit to generate the reset signal if the clock signal is at a constant signal level. 
     
     
       29. The circuit of  claim 26  wherein the memory circuit is operable to store the data during testing of the circuit. 
     
     
       30. A method comprising: 
       
         allowing a functional circuit to operate if a clock signal coupled to the functional circuit has a first predetermined characteristic and if a supply signal coupled to the functional circuit has a first predetermined relationship to a predetermined threshold; and  
       
       
         resetting the functional circuit if the clock signal has a second predetermined characteristic or if the supply signal has a second predetermined relationship to the predetermined threshold. 
       
     
     
       31. The method of  claim 30  wherein: 
       
         allowing the functional circuit to operate comprises allowing the functional circuit to operate if the clock signal has a nonzero frequency and if the supply signal is greater than the predetermined threshold; and  
       
       
         resetting the functional circuit comprises resetting the functional circuit if the clock signal has a zero frequency or if the supply signal is less than the predetermined threshold. 
       
     
     
       32. A method, comprising: 
       
         determining whether a clock signal has a predetermined characteristic;  
       
       
         determining whether a supply signal has a predetermined relationship to a predetermined threshold value; and  
       
       
         resetting a circuit if the clock signal has the predetermined characteristic or if the supply signal has the predetermined relationship. 
       
     
     
       33. The method of  claim 32  wherein: 
       
         determining whether the clock signal has a predetermined characteristic comprises determining whether the clock signal is at a constant signal level; and  
       
       
         determining whether the supply signal has the predetermined relationship to the threshold value comprises determining whether the supply signal is less than the threshold value. 
       
     
     
       34. The method of  claim 32  wherein the resetting comprises: 
       
         generating a reset signal if the clock signal has the predetermined characteristic or if the supply signal has the predetermined relationship to the threshold value; and  
       
       
         coupling the reset signal to the circuit. 
       
     
     
       35. A method, comprising: 
       
         receiving a clock signal;  
       
       
         generating a reset signal if the clock signal has a predetermined characteristic; and  
       
       
         resetting a processor with the reset signal to prevent the processor from altering data stored in a memory circuit. 
       
     
     
       36. The method of  claim 35 , further comprising storing the data in the memory circuit during testing of a circuit that includes the processor and the memory circuit. 
     
     
       37. The clock detector of  claim 12  wherein the circuit is operable to: 
       
         generate the first signal if the clock signal is present; and  
       
       
         generate the second signal if the clock signal is absent. 
       
     
     
       38. The circuit of  claim 17  wherein the supply signal comprises a supply voltage.