Two-stage amplifier for active pixel sensor cell array for reducing fixed pattern noise in the array output

Abstract

An active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell. The two-stage amplifier design reduces fixed pattern noise in the image data generated by reading the array, by providing increased gain for the output of each cell without impractically increasing the size and complexity of each cell. For each column of cells of the array, one part of the two-stage amplifier for each cell is shared by all cells of the column, and another part of the two-stage amplifier for each cell is included within the cell itself. Preferably, each cell includes only NMOS transistors (no cell includes a PMOS transistor). In preferred embodiments, a differential amplifier within each cell is the primary stage of the cell's output amplifier, PMOS load circuitry including a secondary output amplifier stage is shared by all cells of the column, and the two amplifier stages for each cell together comprise an op amp. In some such preferred embodiments, the op amp is provided with capacitor feedback for increased gain. Another aspect of the invention is an active pixel sensor cell including a differential amplifier, and PMOS transistor load circuitry coupled to the cell. Preferably, the differential amplifier is the first stage of an op amp, and the remainder of the op amp, including optional capacitor feedback circuitry, is coupled to the cell but is not included within the cell.

What is claimed is:  
     
       1. An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising: 
       a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;  
       a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier; and  
       load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the primary amplifier stage and the load circuitry together comprise an op amp, and the op amp has an output terminal at which the further amplified signal is output, wherein the primary amplifier stage has a first input coupled to the first photodiode and a second input to which the output terminal of the op amp is coupled, and wherein the array is operable in a mode in which the further amplified signal is output at the output terminal of the op amp and is fed back to the second input of the primary amplifier stage.  
     
     
       2. An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising: 
       a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;  
       a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier; and  
       load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the primary amplifier stage and the load circuitry together comprise an op amp, and the op amp has an output terminal at which the further amplified signal is output, wherein the primary amplifier stage has a first input coupled to the first photodiode and a second input, and the array also includes:  
       a capacitor feedback circuit having an output coupled to the second input of the primary amplifier stage, and an input coupled to the output terminal of the op amp.  
     
     
       3. An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising: 
       a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;  
       a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier; and  
       load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein each of the primary amplifier stage and the second primary amplifier stage includes NMOS transistors but no PMOS transistor, wherein the column includes a first column line, a second column line, a third column line, and a fourth column line, and wherein the load circuitry includes:  
       a first PMOS transistor having a source for coupling to a supply voltage, a drain coupled to a first end of the first column line, and a gate;  
       a second PMOS transistor having a source for coupling to the supply voltage, a drain coupled to a first end of the second column line, and a gate coupled to the gate of the first PMOS transistor and to the drain of the second PMOS transistor;  
       a third PMOS transistor having a gate coupled to a second end of the first column line, a source for coupling to the supply voltage, and a drain at which the further amplifier signal is output;  
       a first NMOS transistor having a drain coupled to the drain of the third PMOS transistor, a source for coupling to ground potential, and a gate; and  
       bias circuitry coupled to the gate of the first NMOS transistor and configured to output a bias voltage to said gate of the first NMOS transistor.  
     
     
       4. The array of  claim 3 , wherein the reset circuit of the first cell and the second reset circuit of the second cell are coupled to the first column line, the primary amplifier stage has a first input coupled to the first photodiode, a second input coupled to the third column line, and a tail current circuit coupled to the fourth column line and configured to sink a first tail current to said fourth column line in response to a row select signal, 
       the second primary amplifier stage has a first input coupled to the second photodiode, a second input coupled to the third column line, and a second tail current circuit coupled to the fourth column line and configured to sink a second tail current to said fourth column line to response to another row select signal, and wherein the load circuitry also includes:  
       a second NMOS transistor having a drain coupled to the fourth column line, a source for coupling to the ground potential, and a gate coupled to the bias circuitry.  
     
     
       5. An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising: 
       a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;  
       a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier; and  
       load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the column includes at least a first column line, and the load circuitry includes:  
       a PMOS transistor having a gate coupled to an end of the first column line, a source for coupling to a supply voltage, and a drain at which the further amplified signal is output;  
       a first NMOS transistor having a drain coupled to the drain of the PMOS transistor, a source for coupling to ground potential, and a gate; and  
       a bias circuit coupled to the gate of the first NMOS transistor and configured to output a bias voltage to the gate of the first NMOS transistor in response to a bias control signal, wherein the bias voltage undergoes a first transition which rapidly turns off the first NMOS transistor in response to transition of the bias control signal from a first level to a second level, and the bias voltage undergoes a second transition causing the first NMOS transistor to conduct a desired bias current in response to transition of the bias control signal from the second level to the first level.  
     
     
       6. The array of  claim 5 , wherein the column also includes a second column line, a third column line, and a fourth column line, the reset circuit of the first cell and the second reset circuit of the second cell are coupled to the first column line, the primary amplifier stage has a first input coupled to the first photodiode, a second input coupled to the third column line, and a tail current circuit coupled to the fourth column line and configured to sink a first tail current to said fourth column line in response to a row select signal, the second primary amplifier stage has a first input coupled to the second photodiode, a second input coupled to the third column line, and a second tail current circuit coupled to the fourth column line and configured to sink a second tail current to said fourth column line in response to another row select signal, and wherein the load circuitry includes: 
       a second PMOS transistor having a source for coupling to the supply voltage, a drain coupled to another end of the first column line, and a gate;  
       a third PMOS transistor having a source for coupling to the supply voltage, a drain coupled to a first end of the second column line, and a gate coupled to the gate of the second PMOS transistor and to the drain of the third PMOS transistor; and  
       a second NMOS transistor having a drain coupled to the fourth column line, a source for coupling to ground potential, and a gate coupled to the bias circuitry to receive said bias voltage from the bias circuitry.  
     
     
       7. An active pixel sensor cell array including at least a first cell and a second cell connected along a column including at least a first column line, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising: 
       a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;  
       a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode; and  
       load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the load circuitry includes:  
       a PMOS transistor having a gate coupled to an end of the first column line, a source for coupling to a supply voltage, and a drain at which the further amplified signal is output;  
       a first NMOS transistor having a drain coupled to the drain of the PMOS transistor, a source for coupling to ground potential, and a gate; and  
       a bias circuit coupled to the gate of the first NMOS transistor and configured to output a bias voltage to the gate of the first NMOS transistor in response to a bias control signal, wherein the bias voltage undergoes a first transition which rapidly turns off the first NMOS transistor in response to transition of the bias control signal from a first level to a second level, and the bias voltage undergoes a second transition causing the first NMOS transistor to conduct a desired bias current in response to transition of the bias control signal from the second level to the first level.  
     
     
       8. The array of  claim 7 , wherein the column also includes a second column line, a third column line, and a fourth column line, the primary amplifier stage is a first differential amplifier, the second primary amplifier stage is a second differential amplifier, the reset circuit of the first cell and the second reset circuit of the second cell are coupled to the first column line, the first differential amplifier has a first input coupled to the first photodiode, a second input coupled to the third column line, and a tail current circuit coupled to the fourth column line and configured to sink a first tail current to said fourth column line in response to a row select signal, the second differential amplifier has a first input coupled to the second photodiode, a second input coupled to the third column line, and a second tail current circuit coupled to the fourth column line and configured to sink a second tail current to said fourth column line in response to another row select signal, and wherein the load circuitry includes: 
       a second PMOS transistor having a source for coupling to the supply voltage, a drain coupled to another end of the first column line, and a gate;  
       a third PMOS transistor having a source for coupling to the supply voltage, a drain coupled to a first end of the second column line, and a gate coupled to the gate of the second PMOS transistor and to the drain of the third PMOS transistor; and  
       a second NMOS transistor having a drain coupled to the fourth column line, a source for coupling to ground potential, and a gate coupled to the bias circuitry to receive said bias voltage from the bias circuitry.  
     
     
       9. The array of  claim 7 , wherein the primary amplifier stage is a first differential amplifier, the second primary amplifier stage is a second differential amplifier, the first differential amplifier and the load circuitry together comprise an op amp, and the op amp has an output terminal at which the further amplified signal is output. 
     
     
       10. The array of  claim 9 , wherein the first differential amplifier has a first input coupled to the first photodiode and a second input to which the output terminal of the op amp is coupled, and wherein the array is operable in a mode in which the further amplified signal is output at the output terminal of the op amp and is fed back to the second input of the first differential amplifier. 
     
     
       11. An active pixel sensor cell circuit, including 
       an active pixel sensor cell including a photodiode, a reset circuit coupled to the photodiode and configured to reset the first photodiode in response to a reset signal, and a differential amplifier coupled to the photodiode and configured to output an amplified signal indicative of a sampled output voltage of said photodiode in response to a control signal; and  
       load circuitry physically separate from the active pixel sensor cell, wherein the load circuitry is coupled to the differential amplifier for receiving the amplified signal amplifier stage, and the load circuitry includes a secondary output amplifier stage configured to output a further amplified signal in response to the amplified signal, wherein the differential amplifier and the secondary output amplifier stage together comprise an op amp, and the op amp has an output terminal at which the further amplified signal is output, wherein the differential amplifier has a first input coupled to the photodiode and a second input to which the output terminal of the op amp is coupled, and wherein the circuit is operable in a mode in which the further amplified signal is output at the output terminal of the op amp and is fed back to the second input of the differential amplifier.  
     
     
       12. An active pixel sensor cell circuit, including: 
       an active pixel sensor cell including a photodiode, a reset circuit coupled to the photodiode and configured to reset the first photodiode in response to a reset signal, and a differential amplifier coupled to the photodiode and configured to output an amplified signal indicative of a sampled output voltage of said photodiode in response to a control signal; and  
       load circuitry physically separate from the active pixel sensor cell, wherein the load circuitry is coupled to the differential amplifier for receiving the amplified signal amplifier stage, and the load circuitry includes a secondary output amplifier stage configured to output a further amplified signal in response to the amplified signal, wherein the differential amplifier and the secondary output amplifier stage together comprise an op amp, and the op amp has an output terminal at which the further amplified signal is output, wherein the differential amplifier has a first input coupled to the photodiode and a second input, and wherein said active pixel sensor cell circuit also includes:  
       a capacitor feedback circuit having an output coupled to the second input of the differential amplifier, and an input coupled to the output terminal of the op amp.  
     
     
       13. An active pixel sensor cell circuit, including: 
       an active pixel sensor cell including a photodiode, a reset circuit coupled to the photodiode and configured to reset the first photodiode in response to a reset signal, and a differential amplifier coupled to the photodiode and configured to output an amplified signal indicative of a sampled output voltage of said photodiode in response to a control signal;  
       load circuitry physically separate from the active pixel sensor cell, wherein the load circuitry is coupled to the differential amplifier for receiving the amplified signal amplifier stage, and the load circuitry includes a secondary output amplifier stage configured to output a further amplified signal in response to the amplified signal; and  
       a first column line extending through the cell, a second column line extending through the cell, a third column line extending through the cell, and a fourth column line extending through the cell, wherein the reset circuit is coupled to the first column line,  
       wherein the differential amplifier has a first input coupled to the photodiode, a second input coupled to the third column line, and a tail current circuit coupled to the fourth column line and configured to sink a first tail current to said fourth column line in response to a row select signal, and wherein the load circuitry includes:  
       a first PMOS transistor having a source for coupling to a supply voltage, a drain coupled to a first end of the first column line, and a gate;  
       a second PMOS transistor having a source for coupling to the supply voltage, a drain coupled to a first end of the second column line, and a gate coupled to the gate of the first PMOS transistor and to the drain of the second PMOS transistor;  
       a third PMOS transistor having a gate coupled to a second end of the first column line, a source for coupling to the supply voltage, and a drain at which the further amplified signal is output;  
       a first NMOS transistor having a drain coupled to the drain of the third PMOS transistor, a source for coupling to ground potential, and a gate; and  
       bias circuitry coupled to the gate of the first NMOS transistor and configured to output a bias voltage to said gate of the first NMOS transistor.  
     
     
       14. The active pixel sensor cell circuit of  claim 13 , wherein the load circuitry also includes: 
       a second NMOS transistor having a drain coupled to the fourth column line, a source for coupling to the ground potential, and a gate coupled to the bias circuitry for receiving the bias voltage from said bias circuitry.  
     
     
       15. An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising: 
       
         a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;  
       
       
         a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier; and  
       
       
         load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the primary amplifier stage has a first input coupled to the first photodiode and a second input, and wherein the array is operable in a mode in which the further amplified signal is output and is fed back to the second input of the primary amplifier stage. 
       
     
     
       16. An active pixel sensor cell array including at least a first cell and a second cell connected along a column, where the first cell is an active pixel sensor cell including a first photodiode and a reset circuit configured to reset the first photodiode in response to a reset signal, and the second cell is an active pixel sensor cell including a second photodiode and a second reset circuit configured to reset the second photodiode in response to a second reset signal, said array comprising: 
       
         a primary amplifier stage within the first cell, coupled to the first photodiode and configured to output a first amplified signal indicative of a sampled output voltage of said first photodiode;  
       
       
         a second primary amplifier stage within the second cell, coupled to the second photodiode and configured to output a second amplified signal indicative of a sampled output voltage of said second photodiode, wherein each of the primary amplifier stage and the second primary amplifier stage is a differential amplifier; and  
       
       
         load circuitry, physically separate from the first cell and the second cell but coupled to both the primary amplifier stage and the second primary amplifier stage, including a secondary output amplifier stage configured to output a further amplified signal in response to any selected one of the first amplified signal and the second amplified signal, wherein the primary amplifier stage has a first input coupled to the first photodiode and a second input, and the array also includes:  
       
       
         a capacitor feedback circuit having an output coupled to the second input of the primary amplifier stage, and an input coupled to further amplified signal. 
       
     
     
       17. The array of  claim 7 , wherein the column also includes a second column line, a third column line, and a fourth column line, the primary amplifier stage is a first differential amplifier, the second primary amplifier stage is a second differential amplifier, the reset circuit of the first cell and the second reset circuit of the second cell are coupled to the first column line, the first differential amplifier has a first input coupled to the first photodiode, a second input coupled to the third column line, and a tail current circuit coupled to the fourth column line and configured to sink a first tail current to said fourth column line in response to a row select signal, the second differential amplifier has a first input coupled to the second photodiode, a second input coupled to the third column line, and a second tail current circuit coupled to the fourth column line and configured to sink a second tail current to said fourth column line in response to another row select signal, and wherein the load circuitry includes: 
       
         a second PMOS transistor having a source for coupling to the supply voltage, a drain coupled to another end of the first column line, and a gate;  
       
       
         a third PMOS transistor having a source for coupling to the supply voltage, a drain coupled to a first end of the second column line, and a gate coupled to the gate of the second PMOS transistor and to the drain of the third PMOS transistor; and  
       
       
         a second NMOS transistor having a drain coupled to the fourth column line, a source for coupling to ground potential, and a gate coupled to the bias circuitry to receive said bias voltage from the bias circuitry. 
       
     
     
       18. The array of  claim 7 , wherein the primary amplifier stage is a first differential amplifier, the second primary amplifier stage is a second differential amplifier. 
     
     
       19. The array of  claim 18 , wherein the first differential amplifier has a first input coupled to the first photodiode and a second input, and wherein the array is operable in a mode in which the further amplified signal is output and is fed back to the second input of the first differential amplifier. 
     
     
       20. An active pixel sensor cell circuit, including 
       
         an active pixel sensor cell including a photodiode, a reset circuit coupled to the photodiode and configured to reset the first photodiode in response to a reset signal, and a differential amplifier coupled to the photodiode and configured to output an amplified signal indicative of a sampled output voltage of said photodiode in response to a control signal; and  
       
       
         load circuitry physically separate from the active pixel sensor cell, wherein the load circuitry is coupled to the differential amplifier for receiving the amplified signal amplifier stage, and the load circuitry includes a secondary output amplifier stage configured to output a further amplified signal in response to the amplified signal, wherein the differential amplifier has a first input coupled to the photodiode and a second input, and wherein the circuit is operable in a mode in which the further amplified signal is output and is fed back to the second input of the differential amplifier. 
       
     
     
       21. An active pixel sensor cell circuit, including: 
       
         an active pixel sensor cell including a photodiode, a reset circuit coupled to the photodiode and configured to reset the first photodiode in response to a reset signal, and a differential amplifier coupled to the photodiode and configured to output an amplified signal indicative of a sampled output voltage of said photodiode in response to a control signal; and  
       
       
         load circuitry physically separate from the active pixel sensor cell, wherein the load circuitry is coupled to the differential amplifier for receiving the amplified signal amplifier stage, and the load circuitry includes a secondary output amplifier stage configured to output a further amplified signal in response to the amplified signal, wherein the differential amplifier has a first input coupled to the photodiode and a second input, and wherein said active pixel sensor cell circuit also includes:  
       
       
         a capacitor feedback circuit having an output coupled to the second input of the differential amplifier, and an input coupled to the further amplified signal. 
       
     
     
       22. A pixel sensor, comprising: 
       
         a photodetector; and  
       
       
         a differential pair of transistors having a first input coupled to said photodetector, a second input coupled to an input column line, a first differential output coupled to a first output column line, and a second differential output coupled to a second output column line. 
       
     
     
       23. The pixel sensor of  claim 22 , further comprising a switch configured to activate said differential pair, said switch coupled to a row line. 
     
     
       24. A pixel sensor, comprising: 
       
         a photodetector; and  
       
       
         an amplifier having an input coupled to said photodetector, a first complementary output coupled to a first output column line, and a second complementary output coupled to a second output column line. 
       
     
     
       25. The pixel sensor of  claim 24 , further comprising a switch configured to activate said amplifier, said switch coupled to a row line.