Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip

Abstract

The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the emitter of the transistor of the integrated control circuit.

We claim:  
     
       1. A manufacturing  process for manufacturing a monolithic semiconductor device comprising  that includes at least one transistor of an integrated control circuit and one power transistor integrated on the same chip, the phases of which envisage  steps comprising: 
       the epitaxial growth(a) epitaxially growing on a semiconductor substrate ( 11 )  of a first type of conductivity, of  a semiconductor layer ( 22 )  which is also of the aforesaid first type  the same type of conductivity as said semiconductor substrate;  
       the simultaneous formation,(b) simultaneously forming by diffusion of doping agent within the surface of the layer ( 22 ), of  a first semiconductor region ( 23 )  of a second type of conductivity and a second semiconductor region ( 24 )  of a  said second type of conductivity, said first region ( 23 )  constituting the base region of the power transistor, said second region ( 24 )  constituting the horizontal insulating region of the integrated control circuit with respect to the power transistor;  
       the simultaneous formation,(c) simultaneously forming by diffusion within the surface of the aforesaid regions ( 23 ) and ( 24 )  said first and second regions, of  two other regions ( 25 )  and ( 26 ) , respectively, of the first type of conductivity, constituting, respectively, the emitter region of the power transistor and the buried layer of the collector region of the integrated control circuit transistor;  
       the formation(d) forming, by further subsequent superficial diffusions, of thea base ( 15 )  and the  an emitter ( 16 )  of the aforesaid  said transistor of the integrated control circuit;  
       the formation(e) forming, by simultaneous diffusion, of  connecting regions ( 21 )  and ( 19 ),  at the  a surface ( 12 ) of  the horizontal insulating region ( 24 )  and base region ( 23 )  of the power transistor, respectively;  
       the formation(f) forming, by simultaneous diffusion, of  enrichment regions ( 13 ) and ( 14 )  for the  said emitter ( 25 ) of the power transistor and the buried layer ( 26 )  of the power transistor and said base of the integrated control circuit transistor, respectively ; and  
       characterized by the fact that the formation of the regions ( 21 ), ( 19 ), ( 13 ) and ( 14 ) of the base ( 15 ) and of the emitter ( 16 ) of the transistor of the integrated control circuit is preceded by the epitaxial growth of a semiconductor layer ( 17 ) of the first type of conductivity.  
       (g) epitaxially growing another semiconductor layer of the first type of conductivity before the performing the steps of forming the regions in steps (d), (e) and (f).  
     
     
       2. A manufacturing process as claimed in  claim 1 characterized by the fact that the region ( 15 ) of the base of aforesaid integrated control circuit transistor extends  including the step of extending from the surface ( 12 )  of aforesaid  said another semiconductor layer ( 17 )  as far as the buried layer ( 26 )  of the  said collector region of said integrated control circuit transistor. 
     
     
       3. A process for manufacturing a monolithic semiconductor device that includes a three region vertical structure and a power transistor integrated on the same chip, the steps comprising: 
       (a) epitaxially growing on a semiconductor substrate of a first type of conductivity a semiconductor layer which is the same type of conductivity as said semiconductor substrate; 
       (b) simultaneously forming within the surface of said semiconductor layer a first semiconductor region of a second type of conductivity and a second semiconductor region of said second type of conductivity, said first region constituting a base region of the power transistor, said second region constituting a horizontal insulating region for a portion of the integrated circuit; 
       (c) simultaneously forming within the surface of said first and second regions two other regions of the first type of conductivity, constituting, respectively, the emitter region of the power transistor and a buried layer; 
       (d) epitaxially growing a second semiconductor layer of said first type of conductivity, at least a portion of said second layer being above and next to said buried layer thereby becoming a bottom region of said three region vertical structure; 
       (e) forming a third region of said second conductivity type in said second layer, at least a portion of said third region being above and next to said bottom region of the three region vertical structure, said third region thereby becoming a middle layer of said three region vertical structure; 
       (f) forming a fourth region of said first conductivity type in said middle region, said fourth region thereby becoming a top region of the three region vertical structure; and 
       (g) simultaneously forming connecting regions from the top surface of said second layer to said horizontal insulating region and to said base region of the power transistor respectively.  
     
     
       4. A manufacturing process as claimed in  claim 3  including the step of forming a connecting region from the top surface of said second layer to said buried layer.