System for and method of efficiently controlling memory accesses in a multiprocessor computer system

Abstract

A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

What is claimed is:  
     
       1. A memory system for a computer system having a plurality of processors, the memory system comprising: 
       a data storage device having address and data inputs, outputs, a command input, a plurality of memory lines, and a bit field portion, each memory line having a tag field portion for holding a processor identification code when not being used to hold data and having a check field portion for holding a GONE code, the bit field portion having at least one bit for each memory line for holding a flag indicates whether the tag field portion of the memory line holds said processor identification code; and  
       a memory controller having inputs and outputs coupled to communicate commands, addresses, and data with the processors, the memory controller coupled to the data storage device for storing and retrieving data and processor identification codes in the tag field portions of the memory lines, said GONE code in the check field portion of a memory line when the tag field portion thereof contains said processor identification code, and the flags in the bit field portion of the data storage device, the memory controller using information received from the processors to determine the appropriate updating of the flags for properly indicating which tag field portions contain said processor identification code;  
       wherein the memory controller further comprises:  
       a data buffer, having inputs and outputs coupled to the data inputs and outputs of the data storage device, for receiving and outputting data;  
       an address buffer, having inputs coupled to the plurality of processors, and having inputs and outputs coupled to the address inputs of the data storage device, for receiving addresses; and  
       a memory sequencer, having inputs and outputs, the outputs coupled to control input of the data storage device, the address buffer, and the data buffer, generating signals that instruct the data storage device to store and retrieve said data and said processor identification codes for updating the bit field portion of the data storage device.  
     
     
       2. The memory system of  claim 1 , further comprising a plurality of t bit fields, each t bit field being assigned to a corresponding memory line for confirming whether the tag field portion of said memory line holds a processor identification code. 
     
     
       3. The memory system of  claim 1 , wherein each memory line further comprises a g bit field for confirming whether the check field portion of the memory line holds the GONE code, thereby indicating whether the tag field portion of the memory line holds a processor identification code. 
     
     
       4. The memory system of  claim 3 , wherein a g bit field is one or more bits of a memory line, and wherein the bit field portion comprises a plurality of d bit fields, with each memory line having an assigned d bit field for holding data for the portion of the memory line occupied by the g bit field. 
     
     
       5. The memory system of  claim 1 , wherein a memory line has an address, and wherein the GONE code for the memory line is a result of a hashing function applied to the address of the memory line. 
     
     
       6. The memory system of  claim 1 , wherein the memory sequencer contains combinational logic. 
     
     
       7. The memory system of  claim 1 , wherein each memory line of the data storage device has an unique address and the GONE code is based on the address. 
     
     
       8. The memory system of  claim 7 , wherein the GONE code held in the check field of a memory line is a result of a hashing function performed on the address of the memory line. 
     
     
       9. A method for reading a data storage device having memory lines addressed by memory addresses, the method comprising the steps of: 
       receiving a memory address for requested data and a read command from a processor;  
       retrieving from the data storage device information held in the memory line addressed by the memory address;  
       generating a GONE code for the memory line;  
       comparing the GONE code to the information retrieved;  
       outputting the information retrieved as the requested data if the GONE code does not match the information retrieved;  
       generating a signal indicating that a processor holds the requested data if the GONE code matches the information retrieved;  
       determining whether a G bit indicates that a processor holds requested data of the memory address, if the GONE code matches the information retrieved;  
       retrieving a D bit if the G bit indicates that a processor does not hold the requested data and the GONE code matches the information retrieved; and  
       outputting the information retrieved as the requested data, with the D bit replacing the G bit, if in the determining step the G bit indicated that a processor does not hold the requested data.  
     
     
       10. The method of  claim 9 , further comprising the steps of: 
       generating a signal indicating that a processor holds the requested data if in the determining step the G bit indicated that a processor holds the requested data; and  
       modifying the information being held in the memory line addressed by the memory address so that it identifies the processor that generated the read command.  
     
     
       11. The method of  claim 9 , wherein the step of outputting comprises the steps of: 
       outputting the information retrieved;  
       storing the GONE code in the memory line addressed by the memory address;  
       storing a G bit in the memory line, the G bit indicating that a processor holds the requested data; and  
       storing the identity of the processor which generated the read command in the memory line.  
     
     
       12. A method for writing a data storage device having memory lines addressed by memory addresses, the method comprising the steps of: 
       receiving a processor identifier, a write command, a memory address, and data from a processor;  
       generating a GONE code for the memory line addressed by the memory address;  
       comparing the GONE code to information being held in the memory line;  
       comparing the processor identifier to the information being held in the memory line if the GONE code matches the information being held in the memory line;  
       generating a first signal indicating that a different processor than the processor that generated the write command owns a right to provide data addressed by the memory address, if the GONE code matches and the processor identifier does not match the information being held in the memory line, otherwise generating a second signal indicating that the processor that generated the write command has a right to write the memory line; and  
       storing the data received in the receiving step in the memory line unless said different processor owns a right to provide data addressed;  
       wherein the step of storing further comprises the steps of:  
       storing the data, received in the receiving step, in the memory line addressed by the memory address;  
       comparing the data, received in the receiving step, to the GONE code for the memory line;  
       recording data value of a G bit taken from the data as a D bit, if the data matches the GONE code for the memory line; and  
       setting the G bit to indicate that the data is not held by the processor if the data matches the GONE code for the memory line.  
     
     
       13. A system for reading a data storage device having memory lines addressed by memory addresses, the system comprising: 
       means for receiving a memory address for requested data and a read command from a processor;  
       means for retrieving from the data storage device information held in the memory line addressed by the memory address;  
       means for generating a GONE code for the memory line;  
       means for comparing the GONE code to the information retrieved;  
       means for outputting the information retrieved as the requested data if the GONE code does not match the information retrieved;  
       means for generating a signal indicating that a processor holds the requested data, if the GONE code matches the information retrieved;  
       means for determining whether a G bit indicates that a processor holds requested data, if the GONE code matches the information retrieved;  
       means for retrieving a D bit if the G bit indicates that a processor does not hold the requested data;  
       means for modifying the G bit equal to the D bit if the G bit indicated that a processor does not hold the requested data; and  
       means for outputting the information retrieved as the requested data, with the modified G bit, if prior to replacement, the G bit indicated that a processor does not hold the requested data.  
     
     
       14. The system of  claim 13 , further comprising: 
       means for generating a signal indicating that a processor holds requested data if in the determining step the G bit indicated that a processor holds the data;  
       means for generating a signal that indicates the processor that holds the requested data; and  
       means for modifying the information being held in the memory line addressed by the memory address so that it identifies the processor that generated the read command.  
     
     
       15. The system of  claim 13 , wherein the means for outputting comprises: 
       means for outputting the retrieved information;  
       means for storing the GONE code in the memory line addressed by the memory address;  
       means for storing a G bit in the memory line, the G bit indicating that a processor holds the requested data; and  
       means for storing the identity of the processor that generated the read command in the memory line.  
     
     
       16. A system for writing a data storage device having memory lines addressed by memory addresses, the system comprising: 
       means for receiving a processor identifier, a write command, a memory address, and data from a processor;  
       means for generating a GONE code for the memory line addressed by the memory address;  
       means for comparing the GONE code to information being held in the memory line;  
       means for comparing the processor identifier to the information being held in the memory line, if the GONE code matches the information being held in the memory line;  
       means for generating a first signal indicating that a different processor than the processor that generated the write command owns a right to provide data addressed by the memory address if the GONE code matches and the processor identifier does not match the information being held in the memory line;  
       means for generating a second signal indicating that the processor that generated the write command has a right to write the memory line if either the GONE code does not match or the processor identifier matches the information being held in the memory line; and  
       means for storing the data received in the receiving step in the memory line unless said different processor owns a right to provide data addressed by the memory address;  
       wherein the means for storing further comprises:  
       means for storing the data, received by the means for receiving, in the memory line addressed by the memory address;  
       means for comparing the data, received by the means for receiving, to the GONE code for the memory line;  
       means for recording data value of a G bit taken from the data as a D bit, if the data matches the GONE code for the memory line; and means for setting the G bit to indicate that the data, received by the means for receiving, is not held by the processor if the data matches the GONE code for the memory line.  
     
     
       17. A memory system for a computer system having a plurality of processors, the memory system comprising: 
       a data storage device comprising a plurality of memory lines, each memory line having a tag field and a check field, the data storage device further including a bit field; and  
       a memory controller coupled to said plurality of processors for communicating read commands, write commands, and data therewith, the memory controller further coupled to the data storage device for reading and writing data in the memory lines thereof, including in the check and tag fields thereof, in response to said commands, and for reading and writing GONE codes and processor identifiers in the check and tag fields respectively when said fields are not holding data from the processors;  
       wherein data from plurality of processors can match the GONE codes of the memory lines, and the memory controller writes in the bit field an indication of authenticity of each GONE code written in the check field, and wherein in response to receiving a command to read the first memory line from first processor, the memory controller further supplies the contents thereof to said first processor in response to the contents of the check field matching the GONE code thereof and the contents of the bit field not authenticating said matching of the GONE code thereof.  
     
     
       18. The memory system of  claim 17 , wherein: 
       in response to receiving a command to read a memory line from a processor, the controller reads the memory line, supplies the contents thereof to the processor in response to the contents of the check field thereof not matching the GONE code thereof, writes the processor identifier of the processor to the tag field thereof, and writes the GONE code thereof in the check field thereof.  
     
     
       19. The memory system of  claim 17 , wherein: 
       in response to receiving a command to write data in a memory line from a processor, the controller reads the check and tag fields thereof, writes the data therein in response to the contents of the check field thereof not matching the GONE code thereof, and writes said data therein in response to the contents of the tag field thereof matching the processor identifier of the processor.  
     
     
       20. A method for writing a data storage device having memory lines addressed by memory addresses, the method comprising the steps of: 
       receiving a processor identifier, a write command, a memory address, and data from a processor;  
       generating a GONE code for the memory line addressed by the memory address;  
       comparing the GONE code to information being held in said memory line;  
       comparing the processor identifier to said information;  
       generating a signal in response to either the GONE code not matching said information or the processor identifier matching said information; and  
       storing the data received in the receiving step in the memory line in response to said signal;  
       wherein the step of storing comprises the steps of:  
       storing the data, received in the receiving step, in the memory line addressed by the memory address;  
       comparing the data, received in the receiving step, to the GONE code for the memory line;  
       recording data value of a G bit taken from the data as a D bit, if the data matches the GONE code for the memory line; and  
       setting the G bit to indicate that the data is not held by a processor if the data matches the GONE code for the memory line.  
     
     
       21. A system for writing a data storage device having memory lines addressed by memory addresses, the system comprising: 
       means for receiving a processor identifier, a write command, a memory address, and data from a processor;  
       means for generating a GONE code for the memory line addressed by the memory address;  
       means for comparing said GONE code to information being held in the memory line;  
       means for comparing the processor identifier to said information;  
       means for generating a signal in response to either the GONE code not matching said information or the processor identifier matching said information; and  
       means for storing the data received in the receiving step in the memory line in response to said signal;  
       wherein the means for storing comprises:  
       means for storing the data, received by the means for receiving, in the memory line addressed by the memory address;  
       means for comparing the data, received by the means for receiving, to the GONE code for the memory line;  
       means for recording data value of a G bit taken from the data as a D bit, if the data matches the GONE code for the memory line; and means for setting the G bit to indicate that the data, received by the means for receiving, is not held by said processor if the data matches the GONE code for the memory line.  
     
     
       22. A method of managing memory access to a data storage in a multi- processor system including a plurality of processors, each processor coupled to a memory cache, each processor having a processor ID, the method comprising:    
       
         receiving from an accessing processor a request to read a memory line of the data storage;  
       
       
         reading the memory line from the data storage;  
       
       
         determining only from the read memory line whether the memory line stores current data, or stores the processor ID of an owner processor holding the current data of the memory line in its memory cache by comparing a first portion of the memory line with a code that indicates that the current data is held in the memory cache of a processor; and  
       
       
         responsive to the determination, providing portions of the memory line to the accessing processor as either the current data, or the processor ID of the owner processor. 
       
     
     
       23. The method of  claim 22 , wherein reading the memory line from the data storage consists of a single memory access. 
     
     
       24. The method of  claim 22 , further comprising: 
       
         providing a control signal to the accessing processor in conjunction with the provided portions of the memory line, for indicating to the accessing processor whether the provided portions include the current data or processor ID of the owner processor. 
       
     
     
       25. The method of  claim 22 , further comprising: 
       
         responsive to determining only from the read memory line that the memory line stores current data, providing the memory line to the accessing processor as data and storing in the memory line the processor ID of the accessing processor as the processor ID of an owner processor holding the data of the memory line in its memory cache; and  
       
       
         responsive to determining only from the read memory line that the memory line stores the processor ID of an owner processor currently holding the current data in its memory cache, providing from the memory line the processor ID of the owner processor to the accessing processor, and storing in the memory line the processor ID of the accessing processor as the processor ID of an owner processor currently holding the data of the memory line in its memory cache. 
       
     
     
       26. The method of  claim 22 , wherein providing portions of the memory line to the accessing processor as current data, further comprises: 
       
         prior to providing the portions of the memory line, setting a portion of the memory line to an actual value of the portion held in a storage area separate from the memory line. 
       
     
     
       27. The method of  claim 22 , further comprising: 
       
         deriving the code from an address of the read memory line. 
       
     
     
       28. The method of  claim 22 , wherein determining only from the read memory line whether the memory line stores current data, or stores the processor ID of an owner processor holding the current data of the memory line in its memory cache, further comprises: 
       
         responsive to the first portion of the memory line matching the code, determining from a second portion of the memory line whether the first portion contains data that incidentally matches the code; and  
       
       
         responsive to the first portion of the memory line containing data that incidentally matches the code, retrieving current data for the second portion, and setting the second portion of the memory line to the current data prior to providing the portions of the memory line to the accessing processor as the current data. 
       
     
     
       29. A method of managing memory access to a data storage in a multi- processor system including a plurality of processors, each processor coupled to a memory cache, each processor having a processor ID, the method comprising:    
       
         receiving from an accessing processor a request to access a memory line of the data storage;  
       
       
         reading the memory line from the data storage;  
       
       
         responsive to the request being a request to read the memory line:  
       
       
         determining only from the read memory line whether the memory line stores current data, or stores the processor ID of an owner processor holding the current data of the memory line in its memory cache by comparing a first portion of the memory line with a code that indicates that the current data is held in the memory cache of a processor; and  
       
       
         responsive to the determination, providing portions of the memory line to the accessing processor as either the current data, or the processor ID of the owner processor; and  
       
       
         responsive to the request being a request to write data to the memory line:  
       
       
         determining only from the read memory line whether the accessing processor ID is an owner processor holding the current data of the memory line in its memory cache, or is another processor; and  
       
       
         responsive to the accessing processor being the owner processor, writing the current data to the memory line. 
       
     
     
       30. The method of  claim 29 , wherein reading the memory line from the data storage consists of a single memory access. 
     
     
       31. A memory circuit for managing memory access to a data storage in a multi- processor system including a plurality of processors, each processor coupled to a memory cache, each processor having a processor ID and coupled to a data bus, the memory circuit comprising:    
       
         a data storage comprising a plurality of memory lines, each memory line adapted to store a plurality of data words;  
       
       
         a memory controller adapted to access a memory line in the data storage in response to a request from an accessing processor, and further adapted to:  
       
       
         receive from an accessing processor a request to read a memory line of the data storage;  
       
       
         read the memory line from the data storage;  
       
       
         determining only from the read memory line whether the memory line stores current data, or stores the processor ID of an owner processor holding the current data of the memory line in its memory cache by comparing a first portion of the memory line with a code that indicates that the current data is held in the memory cache of a processor; and  
       
       
         responsive to the determination, provide portions of the memory line to the accessing processor via the data bus as either the current data, or the processor ID of the owner processor. 
       
     
     
       32. The memory circuit of  claim 31 , wherein the memory controller is adapted to read the memory line from the data storage in a single memory access. 
     
     
       33. The memory circuit of  claim 31 , further comprising: 
       
         a control bus that couples the memory controller to the plurality of processors; and  
       
       
         the memory controller is further adapted to provide a control signal to the accessing processor via the control bus in conjunction with the provided portions of the memory line on the data bus, for indicating to the accessing processor whether the provided portions include the current data or processor ID of the owner processor. 
       
     
     
       34. The memory circuit of  claim 31 , wherein the memory controller is further adapted to: 
       
         responsive to determining only from the read memory line that the memory line stores current data, provide the memory line to the accessing processor as data via the data bus and storing in the memory line the processor ID of the accessing processor as the processor ID of an owner processor holding the data of the memory line in its memory cache; and  
       
       
         responsive to determining only from the read memory line that the memory line stores the processor ID of an owner processor currently holding the current data in its memory cache, provide from the memory line the processor ID of the owner processor to the accessing processor as data via data bus, and store in the memory line the processor ID of the accessing processor as the processor ID of an owner processor currently holding the data of the memory line in its memory cache. 
       
     
     
       35. The memory circuit of  claim 31 , wherein the memory controller is further adapted to: 
       
         prior to providing the portions of the memory line via the data bus to the accessing processor, set a portion of the memory line to an actual value of the portion held in a storage area separate from the memory line. 
       
     
     
       36. The memory circuit of  claim 31 , wherein the memory controller is further adapted to: 
       
         derive the code from an address of the read memory line. 
       
     
     
       37. The memory circuit of  claim 31 , wherein in determining only from the read memory line whether the memory line stores current data, or stores the processor ID of an owner processor holding the current data of the memory line in its memory cache, the memory controller is adapted to: 
       
         responsive to the first portion of the memory matching the code, determine from a second portion of the memory line whether the first portion contains data that incidentally matches the code; and  
       
       
         responsive to the first portion of the memory containing data that incidentally matches the code, retrieve current data for the second portion, and setting the second portion of the memory to the current data prior to providing the portions of the memory line to the accessing processor as the current data. 
       
     
     
       38. A memory circuit for managing memory access to a data storage in a multi- processor system including a plurality of processors, each processor coupled to a memory cache, each processor having a processor ID and coupled to a data bus, the memory circuit comprising:    
       
         a data storage comprising a plurality of memory lines, each memory line adapted to store a plurality of data words;  
       
       
         a memory controller adapted to access a memory line in the data storage in response to a request from an accessing processor, and further adapted to:  
       
       
         receive from an accessing processor a request to access a memory line of the data storage;  
       
       
         read the memory line from the data storage;  
       
       
         responsive to the request being a request to read the memory line:  
       
       
         determining only from the read memory line whether the memory line stores current data, or stores the processor ID of an owner processor holding the current data of the memory line in its memory cache by comparing a first portion of the memory line with a code that indicates that the current data is held in the memory cache of a processor; and  
       
       
         responsive to the determination, provide portions of the memory line to the accessing processor via the data bus as either the current data, or the processor ID of the owner processor;  
       
       
         responsive to the request being a request to write data to the memory line:  
       
       
         determine only from the read memory line whether the accessing processor ID is an owner processor holding the current data of the memory line in its memory cache, or is another processor; and  
       
       
         responsive to the accessing processor being the owner processor, writing the current data to the memory line. 
       
     
     
       39. The memory circuit of  claim 38 , wherein the memory controller is adapted to read the memory line from the data storage in a single memory access. 
     
     
       40. The memory circuit of  claim 38 , further comprising: 
       
         a control bus that couples the memory controller to the plurality of processors; and  
       
       
         the memory controller is further adapted to provide a control signal to the accessing processor via the control bus in conjunction with the provided portions of the memory line on the data bus, for indicating to the accessing processor whether the provided portions include the current data or processor ID of the owner processor. 
       
     
     
       41. A multiprocessor system, comprising: 
       
         a plurality of processors, each processor coupled to a memory cache, each processor having a processor ID;  
       
       
         a bus coupled to each of the processors, and adapted to transmit requests from the processors for data stored in a memory and data stored in the memory to the processors;  
       
       
         a memory, coupled to the bus, and comprising:  
       
       
         a data storage comprising a plurality of memory lines, each memory line adapted to store a plurality of data words, each memory line including:  
       
         a )  a first portion that can be either:    
         i )  a code for indicating that the data words of the memory line are currently held in the memory cache of one of the processors, or    
         ii )  data for processing; and    
         b )  a second portion that can be either:    
         i )  the processor ID of an owner processor currently holding the data words from the memory line in its memory cache; or    
         ii )  data for processing;    
       
         a memory controller adapted to access a memory line in the data storage in response to a request from an accessing processor, and further adapted to:  
       
         i )  if the first portion does not contain the code, then provide the first and second portions of the memory line as data to the accessing processor via the bus, store the code in the first portion of the memory line, and store the processor ID of the accessing processor in the second portion of the memory line as the processor ID of an owner processor; and    
         ii )  if the first portion contains the code, then provide the processor ID of the owner processor from the second portion of the memory line to the accessing processor via the bus, and store the processor ID of the accessing processor in the second portion of the memory line as the owner processor.   
     
     
       42. The system of  claim 41 , wherein: 
       
         each memory line further includes a third portion adapted to store a bit indicating whether the first portion contains the code or contains data; and  
       
       
         the data storage includes a storage area separate from the memory lines, that stores for each memory line, a corresponding data field holding the actual bit value of the third portion of the memory line;  
       
       
         wherein the memory controller is further adapted to:  
       
         iii )  if the first portion contains the code and the third portion stores a bit indicating that the first portion contains data, set the third portion to the actual bit value stored in the data field corresponding to the memory line, provide the first, second, and third portions of the memory line to the accessing processor via the bus, store the code in the first portion of the memory line, and store the processor ID of the accessing processor in the second portion of the memory line as the processor ID of the owner processor.   
     
     
       43. A multiprocessor system, comprising: 
         a )  a plurality of processors, each processor coupled to a memory cache, each processor having a processor ID;    
         b )  a bus coupled to each of the processors, and adapted to transmit requests from the processors for data stored in a memory and data stored in the memory to the processors;    
         c )  a memory, coupled to the bus, and comprising:    
           1   )  a data storage comprising:    
         a )  a plurality of memory lines, each memory line adapted to store a plurality of data words, each memory line including:    
         i )  a first portion that can be either:    
       
         a first code for indicating that the data words of the memory line are currently held in the memory cache of one of the processors, or  
       
       
         data for processing by one of the processors; and  
       
         ii )  a second portion that can be either:    
       
         the processor ID of an owner processor currently holding the data words from the memory line in its memory cache; or  
       
       
         data for processing;  
       
         iii )  a third portion that can be either:    
       
         an owned code indicating that the memory line is data;  
       
       
         data for processing;  
       
         b )  a storage area separate from the memory lines, and including for each memory line a corresponding data field that stores an actual data value of the third portion of the memory line;    
           2   )  a memory controller adapted to access a memory line in the data storage in response to a read request from an accessing processor, and further adapted to:    
         i )  if first portion does not contain the first code, then provide the memory line to the accessing processor, set the accessing processor as the owner processor by storing the processor ID in the second portion, and store a new code in the first portion;    
         ii )  if the first portion does contain the code and the third portion does not stores the owned code, set the third portion of the memory line to the actual value of the third portion stored in the corresponding data field in the separate storage area, the provide the first, second, and third portions of the memory line to the accessing processor as data, set the accessing processor as the owner processor by storing the processor ID of the accessing processor in the second portion of the memory line, and store the first code in the first portion of the memory line; and    
         iii )  if the first portion does contain first code and the third portion does store then owned code, and the accessing processor is not the owner processor, then provide the accessing processor with the processor ID of the owner processor from the second portion of the memory line, and set the accessing processor as the owner processor by storing the processor ID of the accessing processor in the second portion of the memory line.   
     
     
       44. A multiprocessor system, comprising: 
         a )  a plurality of processors, each processor coupled to a memory cache, each processor having a processor ID;    
         b )  a bus coupled to each of the processors, and adapted to transmit requests from the processors for data stored in a memory and data stored in the memory to the processors;    
         c )  a memory, coupled to the bus, and comprising:    
           1   )  a data storage comprising:    
         a )  a plurality of memory lines, each memory line adapted to store a plurality of data words, each memory line including:    
       
         a first portion that can be either:  
       
         i )  a first code for indicating that the data words of the memory line are currently held in the memory cache of one of the processors, or    
         ii )  data for processing by one of the processors; and    
       
         a second portion that can be either:  
       
         i )  the processor ID of an owner processor currently holding the data words from the memory line in its memory cache; or    
         ii )  data for processing;    
       
         a third portion that can be either:  
       
         i )  an owned code indicating that the memory line is data;    
         ii )  data for processing;    
         b )  a storage area separate from the memory lines, and including for each memory line a corresponding data field that stores an actual data value of the third portion of the memory line;    
           2   )  a memory controller adapted to access a memory line in the data storage in response to a write request from an accessing processor, and further adapted to:    
       
         if the first portion contains the first code, the third portion stores the owned code, and the second portion stores the processor ID of the accessing processor, store updated data words from the accessing processor in the memory line; and  
       
         if the first portion contains the first code, the third portion stores the owned code, and the second portion stores the processor ID of a non - requesting processor, then perform no update on the memory line, in order to prevent the memory line from storing invalid data.