Current limitation programmable circuit for smart power actuators

Abstract

A circuit for limitation of maximum current delivered by a power transistor comprises: a network for detection of the current delivered by the power transistor which generates a first electrical signal; a reference network for generating a reference current proportional to a resistor and self-limited, provided by means of a current generator circuit and a limiting circuit with current mirror; and an operational amplifier which compares the first electrical signal with the reference current and which tends to inhibit the power transistor if the current delivered exceeds a certain threshold value.

What is claimed is:  
     
       1. A circuit for limitation of the maximum current delivered by a power transistor having at least one control terminal and two principal conduction terminals which identify a principal conduction path, comprising: 
       a network for detection of the current delivered by the power transistor coupled with the principal conduction path of the power transistor to generate a first electrical signal proportional to said current,  
       a reference network, for generating a second reference electrical signal, inserted between a first and a second power supply pole and comprising the series of at least one resistor and a reference current generator which generates a reference current self-limited and proportional to a third electrical reference signal, and  
       a comparison network for comparing said first and second electrical signals and driving, by means of an output signal dependent upon said first and second signals, the control terminal of the power transistor,  
       wherein said generator of a reference current comprises the series of a current generator circuit which generates a current proportional to said third electrical reference signal and a current mirror circuit designed to limit the maximum current delivered by the current generator circuit. 
     
     
       2. A circuit in accordance with  claim 1 , wherein the current generator circuit has a first and a second conduction terminal and a reference input terminal for receiving said third electrical reference signal and comprises: 
       an operational amplifier having a first input terminal connected to the reference input, a second input terminal connected to said second conduction terminal and an output terminal, and  
       a first transistor having a control terminal connected to the output terminal of the operational amplifier and two principal conduction terminals connected respectively to said first and second conduction terminals.  
     
     
       3. A circuit in accordance with  claim 2 , wherein the first input terminal of the operational amplifier is an input of the non-inverting type and the second input terminal of the operational amplifier is an input of the inverting type. 
     
     
       4. A circuit in accordance with  claim 3 , wherein the first transistor is a transistor of the MOS n-channel type. 
     
     
       5. A circuit in accordance with  claim 1 , wherein the current mirror circuit comprises a primary leg consisting of a second transistor in which flows a current generated by a current generator and a secondary leg consisting of a third transistor in which flows the reference current. 
     
     
       6. A circuit in accordance with  claim 5 , wherein the second transistor and the third transistor are transistors of the MOS n-channel type. 
     
     
       7. A power actuator of the intelligent type comprising: 
       at least one power transistor having at least one control terminal and two principal conduction terminals which identify a principal conduction path, and  
       a circuit for limitation of the maximum current delivered by the power transistor, comprising:  
       a network for detection of the current delivered by the power transistor coupled with the principal conduction path of the power transistor to generate a first electrical signal proportional to said current,  
       a reference network for generating a second electrical reference signal inserted between a first and a second power supply pole comprising the series of at least one resistor and one reference current generator which generates a reference current self-limited and proportional to a third electrical reference signal,  
       a comparison network for comparing said first and second electrical signals and driving by means of an output signal dependent upon said first and second signals the control terminal of the power transistor,  
       and wherein said reference current generator comprises the series of a current generator circuit which generates a current proportional to said third electrical reference signal and a current mirror circuit designed to limit the maximum current delivered by the current generator circuit. 
     
     
       8. A power actuator in accordance with  claim 7 , wherein the current generator circuit has a first and a second conduction terminals and a reference input terminal for receiving said third electrical reference signal and comprises: 
       an operational amplifier having a first input terminal connected to the reference input and a second input terminal connected to said second conduction terminal and an output terminal, and  
       a first transistor having a control terminal connected to the output terminal of the operational amplifier ( 7 ) and two principal conduction terminals connected respectively to said first and second conduction terminals.  
     
     
       9. A power actuator in accordance with  claim 7  wherein the current mirror circuit comprises a primary leg consisting of a second transistor in which flows a current generated by a current generator and a secondary leg consisting of a third transistor in which flows the reference current. 
     
     
       10. A circuit for limitation of the maximum current delivered by a power transistor having at least one control terminal and two principal conduction terminals which identify a principal conduction path, comprising: 
       
         a network for detection of the current delivered by the power transistor coupled with the principal conduction path of the power transistor to generate a first electrical signal proportional to said current;  
       
         a reference network, for generating a second reference electrical signal, inserted between a first and second power - supply pole and comprising the series of at least one resistor and a reference - current generator which generates a reference current self limited and proportional to a third electrical reference signal;    
       
         a comparison network for comparing said first and second electrical signals and driving, by means of an output signal dependent upon said first and second signals, the control terminal of the power transistor; and  
       
         wherein said reference - current generator comprises the series of a current - generating circuit which generates a current proportional to said third electrical reference signal and a current - limiting circuit designed to limit the maximum current delivered by the current - generating circuit without an error - signal amplifier.    
     
     
       11. The circuit of  claim 10  wherein the current- limiting circuit comprises a primary leg that includes a first transistor through which flows a current generated by a current generator and a secondary leg that includes a second transistor through which flows the reference current.    
     
     
       12. The circuit of  claim 10  wherein the current- limiting circuit comprises a primary leg that includes a first N - channel transistor through which flows a current generated by a current generator and a secondary leg that includes a second N - channel transistor through which flows the reference circuit.    
     
     
       13. An intelligent power actuator, comprising: 
       
         at least one power translator having at least one control terminal and two principal conduction terminals which identify a principal conduction path; and  
       
       
         a circuit for limitation of the maximum current delivered by the power transistor, the circuit comprising,  
       
       
         a network for detection of the current delivered by the power transistor coupled with the principal conduction path of the power transistor to generate a first electrical signal proportional to said current,  
       
         a reference network for generating a second electrical reference signal inserted between a first and a second power - supply pole comprising the series of at least one resistor and one reference - current generator which generates a reference current self - limited and proportional to a third electrical reference signal,    
       
         a comparison network for comparing said first and second electrical signals and drying by means of an output signal dependent upon said first and second signals the control terminal of the power transistor, and  
       
         wherein said reference - current generator comprises the series of a current - generator circuit which generates a current proportional to said third electrical reference signal and a current - limiting circuit designed to limit the maximum current delivered by the current - generator circuit without an error - signal amplifier.    
     
     
       14. The intelligent power actuator of  claim 13  wherein the current- limiting circuit comprises a primary leg that includes a first transistor through which flows a current generated by a current generator and a secondary leg that includes a second transistor through which flows the reference current.    
     
     
       15. A circuit, comprising: 
       
         a first current limiter including a current mirror having a current branch operable to conduct a current and having a limiting branch coupled to the current branch and operable to limit the conducted current to a first level; and  
       
       
         a second current limiter coupled to the first current limiter and including a variable impedance operable to conduct the current and including a control circuit operable to cause the variable impedance to limit the current to a second level that is different than the first level.  
       
     
     
       16. The circuit of  claim 15  wherein the second level is higher than the first level.  
     
     
       17. The circuit of  claim 15  wherein the first current limiter is serially coupled to the second current limiter.  
     
     
       18. The circuit of  claim 15  wherein: 
       
         the current branch of the current mirror comprises a first transistor having a first conduction terminal, a control terminal, and a second conduction terminal, the first transistor operable to conduct the current between the first and second conduction terminals; and  
       
       
         the limiting branch of the current mirror comprises:  
       
       
         a current source coupled to the control terminal of the first transistor; and  
       
       
         a second transistor having a first conduction terminal and a control terminal coupled to the current source and having a second conduction terminal coupled to the second conduction terminal of the first transistor.  
       
     
     
       19. The circuit of  claim 15  wherein: 
       
         the current branch of the current mirror comprises a first transistor of a first size having a first conduction terminal, a control terminal, and a second conduction terminal, the first transistor operable to conduct the current via the first and second conduction terminals; and  
       
       
         the limiting branch of the current mirror comprises:  
       
       
         a current source coupled to the control terminal of the first transistor and operable to generate a limiting current having a maximum level; and  
       
       
         a second transistor of a second size having a first conduction terminal and a control terminal coupled to the current source and a second conduction terminal coupled to the second conduction terminal of the first transistor, the second transistor operable to conduct the limiting current via the first and second terminals and operable to limit the current through the first transistor to the first level, which equals the product of the maximum level of the limiting current and the ratio of the first size to the second size.  
       
     
     
       20. The circuit of  claim 15 , further comprising: 
       
         wherein the variable impedance of the second current limiter comprises a transistor having first and second conduction terminals and a control terminal, the transistor operable to conduct the current via the first and second conduction terminals;  
       
       
         a sense impedance coupled to the second conduction terminal of the transistor and having a value; and  
       
       
         wherein the control circuit comprises an amplifier having a first input terminal operable to receive a reference voltage, a second input terminal coupled to the second conduction terminal of the transistor, and an output terminal coupled to the control terminal of the transistor, the amplifier operable to limit the current through the transistor to the second level, which equals the reference voltage divided by the value of the sense impedance.  
       
     
     
       21. A method, comprising: 
       
         generating a drive current that is related to a substantially constant reference voltage;  
       
       
         limiting the reference voltage to a first level with a voltage limiter; and  
       
       
         limiting the reference voltage to a second level that is different than the first level with a current mirror that is serially coupled to the voltage limiter if the voltage limiter fails to limit the voltage to the first level.  
       
     
     
       22. The method of  claim 21  wherein limiting the reference voltage to a second level comprises limiting the reference voltage to a second level that is higher than the first level if the voltage limiter would otherwise allow the first level to fall below the second level, the reference voltage being measured with respect to a supply node.  
     
     
       23. A circuit comprising: 
       
         a transistor operable to generate a drive current;  
       
         a controller coupled to the transistor, operable to receive a reference current, and operable to control the transistor so as to limit the drive current to a drive - limit level that is related to the reference current; and    
         a reference - current generator coupled to the controller and comprising,    
       
         a first current limiter having no feedback amplifier and operable to provide the reference current to the controller and to limit the reference current to a first level; and  
       
       
         a second current limiter coupled to the first current limiter, operable to generate the reference current, and operable to limit the reference current to a second level that is different than the first level.  
       
     
     
       24. A circuit, comprising: 
       
         a device operable to generate a drive current that is related to a reference current;  
       
       
         a current generator operable to generate the reference current; and  
       
         a current mirror coupled to the current generator at a single non - supply node, operable to conduct the reference current, and operable to limit the reference current to a predetermined level.    
     
     
       25. The circuit of  claim 24  wherein the current mirror comprises a current branch operable to conduct the reference current and having a limiting branch coupled to the current branch and operable to limit the conducted reference current to the predetermined level.  
     
     
       26. The circuit of  claim 24  wherein the current mirror comprises: 
       
         a current source;  
       
       
         a first transistor having a first conduction terminal, a control terminal coupled to the current source, and a second conduction terminal, the first transistor operable to conduct the reference current between the first and second conduction terminals; and  
       
       
         a second transistor having a first conduction terminal and a control terminal coupled to the current source and having a second conduction terminal coupled to the second conduction terminal of the first transistor.  
       
     
     
       27. The circuit of  claim 24  wherein the current mirror comprises: 
       
         a current source for generating a limiting current having a maximum level;  
       
         a first transistor of a first size having a first conduction terminal, a control terminal coupled to the current source, and a second conduction terminal coupled to the single non - supply node, the first transistor operable to conduct the reference current via the first and second conduction terminals; and    
       
         a second transistor of a second size having a first conduction terminal and a control terminal coupled to the current source and a second conduction terminal coupled to the second conduction terminal of the first transistor, the second transistor operable to conduct the limiting current via the first and second terminals and operable to limit the reference current through the first transistor to the predetermined level, which equals the product of the maximum level of the limiting current and the ratio of the first size to the second size.  
       
     
     
       28. The circuit of  claim 24  wherein the current generator comprises: 
         a transistor having a current path coupled to the single non - supply node and having a control terminal, the transistor operable to generate the reference current through the current path;    
       
         a sense impedance coupled to the conduction path of the transistor and having a value; and  
       
       
         an amplifier having a first input terminal operable to receive a reference voltage, a second input terminal coupled to conduction path of the transistor, and an output terminal coupled to the control terminal of the transistor, the amplifier operable to cause the transistor to generate the reference current having a level that equals the reference voltage divided by the value of the sense impedance.  
       
     
     
       29. The circuit of  claim 28  wherein the amplifier is operable to cause the transistor to generate the reference current at a level that is less than the predetermined level.  
     
     
       30. The circuit of  claim 24  wherein the current mirror is serially coupled to the current generator.  
     
     
       31. A circuit, comprising: 
       
         a transistor operable to generate a drive current;  
       
         a controller coupled to the transistor, operable to receive a reference current, and operable to control the transistor so as to limit the drive current to a drive - limit level that is related to the reference current; and    
         a reference - current generator coupled to the controller and comprising,    
       
         a current generator operable to generate the reference current having a first level; and  
       
         a current limiter coupled to the current generator, operable to conduct the reference current, and operable to limit the reference current to a second level that is different than the first level without a negative - feedback amplifier.    
     
     
       32. The circuit of  claim 31  wherein the controller comprises a feedback controller.  
     
     
       33. A circuit, comprising: 
       
         a reference node, an intermediate node, and a first supply node;  
       
       
         a device operable to generate a drive current that is related to a first reference voltage on the reference node;  
       
       
         a voltage limiter coupled between the reference and intermediate nodes and operable to limit the reference voltage on the reference node to a predetermined voltage level; and  
       
         a reference - voltage generator coupled between the intermediate node and the first supply node, coupled to the voltage limiter at and only at the intermediate node, and operable to generate the first reference voltage on the reference node.    
     
     
       34. The circuit of  claim 33  wherein the first reference voltage is higher than the predetermined voltage level when the voltage is measured with respect to ground.  
     
     
       35. The circuit of  claim 33  wherein the voltage limiter is serially coupled to the reference- voltage generator.    
     
     
       36. The circuit of  claim 33  wherein the reference- voltage generator comprises:    
       
         a transistor having first conduction terminal coupled to the intermediate node, a second conduction terminal, and a control terminal, the transistor operable to generate a current through the intermediate node;  
       
       
         a sense impedance coupled between the second conduction terminal of the transistor and the first supply node and having a value; and  
       
       
         an amplifier having a first input terminal operable to receive a second reference voltage, a second input terminal coupled to the second conduction terminal of the transistor, and an output terminal coupled to the control terminal of the transistor, the amplifier operable to cause the transistor to generate the current equal to the second reference voltage divided by the value of the sense impedance.  
       
     
     
       37. The circuit of  claim 33  wherein the voltage limiter comprises: 
       
         a current source;  
       
       
         a first transistor having a first conduction terminal coupled to the intermediate node, a control terminal coupled to the current source, and a second conduction terminal coupled to the reference node, the first transistor operable to conduct a current through the first and second nodes, the current having a first current level;  
       
       
         a second transistor having a first conduction terminal coupled to the intermediate node and having a control terminal and a second conduction terminal coupled to the current source; and  
       
       
         wherein the current source and second transistor are operable to limit the current to a second current level that is different than the first current level.  
       
     
     
       38. The circuit of  claim 33 , further comprising: 
       
         a second supply node; and  
       
       
         an impedance coupled between the reference node and the second supply node.  
       
     
     
       39. A circuit, comprising: 
       
         a transistor operable to generate a drive current;  
       
         a controller coupled to the transistor, operable to receive a reference voltage, and operable to control the transistor so as to limit the drive current to a drive - limit level that is related to the reference voltage; and    
         a reference - voltage generator coupled to the controller and comprising,    
       
         a first voltage limiter operable to provide the reference voltage to the controller and to limit the reference voltage to a first level; and  
       
       
         a second voltage limiter coupled to the first voltage limiter and having no error amplifier, the second voltage limiter operable to limit the reference voltage to a second level that is different than the first level.  
       
     
     
       40. The circuit of  claim 39  wherein the first voltage limiter is serially coupled to the second voltage limiter.  
     
     
       41. A circuit, comprising: 
       
         a node;  
       
       
         a voltage generator coupled to the node and operable to generate a voltage on the node, the voltage having a first voltage level, the voltage generator comprising  
       
       
         a transistor having first conduction terminal coupled to the node, a second conduction terminal, and a control terminal, the transistor operable to generate a current through the node,  
       
       
         a sense impedance coupled to the second conduction terminal of the transistor and having a value, and  
       
       
         an amplifier having a first input terminal operable to receive a reference voltage, a second input terminal coupled to the second conduction terminal of the transistor, and an output terminal coupled to the control terminal of the transistor, the amplifier operable to cause the transistor to generate the current equal to the reference voltage divided by the value of the sense impedance;  
       
       
         a voltage limiter coupled to the node and operable to limit the voltage to a second voltage level that is different than the first voltage level without amplifying an error signal, wherein the voltage limiter comprises,  
       
       
         a current source,  
       
       
         a first transistor having a first conduction terminal coupled to the node, a control terminal coupled to the current source, and a second conduction terminal, the first transistor operable to conduct a current through the node, the current having a first current level,  
       
       
         a second transistor having a first conduction terminal and a control terminal coupled to the current source and having a second conduction terminal coupled to the second conduction terminal of the first transistor, and  
       
       
         wherein the current source and second transistor are operable to limit the current to a second current level that is different than the first current level; and  
       
       
         wherein the voltage generator is serially coupled to the voltage limiter.  
       
     
     
       42. The circuit of  claim 41  wherein the second voltage level is lower than the first voltage level when the voltage is measured with respect to ground.  
     
     
       43. The circuit of  claim 41 , further comprising: 
       
         a supply node; and  
       
       
         an impedance coupled between the node and the supply node.  
       
     
     
       44. A method, comprising: 
       
         generating a reference voltage having a first level with a voltage generator;  
       
       
         generating a drive current;  
       
       
         preventing the drive current from exceeding a level that is related to the reference voltage; and  
       
         preventing the reference voltage from falling below a second level that is lower than the first level with a voltage limiter that is coupled to the voltage generator at a single non - supply node.    
     
     
       45. The method of  claim 44  wherein preventing the reference voltage comprises preventing the reference voltage from falling below the second level if the voltage generator would otherwise generate the voltage at a level lower than the second level.  
     
     
       46. A method, comprising: 
       
         generating a reference voltage having a first level;  
       
       
         generating a drive current;  
       
       
         preventing the drive current from exceeding a predetermined level that is related to the reference voltage; and  
       
       
         preventing the reference voltage from falling below a second level that is lower than the first level with a current mirror.  
       
     
     
       47. A circuit, comprising: 
       
         a transistor operable to generate a drive current;  
       
         a controller coupled to the transistor, operable to receive a reference voltage, and operable to control the transistor so as to limit the drive current to a drive - limit level that is related to the reference voltage; and    
         a reference - voltage generator coupled to the controller and comprising,    
       
         a voltage generator operable to generate the reference voltage having a first level; and  
       
       
         a voltage limiter serially coupled to the voltage generator and operable to limit the reference voltage to a second level that is different than the first level without amplifying an error signal.  
       
     
     
       48. A method, comprising: 
       
         generating a drive current that is proportional to a substantially constant reference current;  
       
         generating the reference current having a first level with a reference - current generator; and    
       
         preventing the reference current from exceeding a second level that is higher than the first level with a current limiter that has no feedback amplifier and that is serially coupled to the current generator.  
       
     
     
       49. A method, comprising: 
       
         generating a drive current that is related to a reference current;  
       
         setting the reference current to a first level with a reference - current generator; and    
         limiting the reference current to a second level that is different than the first level with a current limiter if the reference current exceeds the first level, the current limiter being coupled to the reference - current generator at a single non - supply node.    
     
     
       50. The method of  claim 49  wherein limiting the reference current to a second level comprises limiting the reference current to a second level that is higher than the first level if the reference current exceeds the first level.