Semiconductor switching apparatus and method of controlling a semiconductor switching element

Abstract

An inductance in a path (R 1 ) from a gate electrode ( 3 G) of a GTO ( 3 ) through a gate driver ( 4 ) and a node ( 13 ) to a cathode electrode ( 3 K) is determined so that a turn-off gain may be not more than 1. At a turn-off, a main current (I A ) is entirely commutated from the gate electrode ( 3 G) towards the node ( 13 ) through the gate driver ( 4 ) in a direction reverse to a turn-off control current (I G ) A peak voltage suppressing circuit ( 5 ) clamps an anode-cathode voltage (V A-K ) which rises on, to a prescribed voltage value for a prescribed time. This prevents losses caused by a snubber circuit. Commutation of a main current to the gate prevents locally concentrating in the cathode side of the semiconductor switching element, to thereby increase the turn off capability of the semiconductor switching element. Further, this prevents or reduces dissipation of large amount produced by a discharge of the electric charges from a snubber capacitor. Thus, reduction in dissipation and in size of the whole apparatus can be achieved.

1. A semiconductor switching apparatus, comprising:
 a semiconductor switching element having first, second and third electrodes, for carrying a main current which flows into said first electrode, from said first electrode direct to said second electrode when brought into an on-state in response to a turn-on control current applied to said third electrode; and  
 driving control means connected between said third and second electrodes, for producing said turn-on control current and applying it to said third electrode,  
 wherein said main current is entirely commutated to said driving control means through the first to third electrodes in a direction reverse to said turn-on control current at a turn-off.  
 
     
     
       2. The semiconductor switching apparatus of  claim 1 , further comprising:
 peak voltage suppressing means for holding a voltage between said first and second electrodes to a prescribed voltage value for a prescribed period when said voltage between said first and second electrodes rises and reaches to said prescribed voltage value at said turn-off,  
 wherein said prescribed voltage value is determined within a limit beyond which said voltage between said first and second electrodes exceeds a voltage blocking capability of said semiconductor switching element.  
 
     
     
       3. The semiconductor switching apparatus of  claim 2 , wherein
 said peak voltage suppressing moans is a voltage clamp circuit connected in parallel between the first and second electrodes.  
 
     
     
       4. The semiconductor switching apparatus of  claim 1 , further comprising:
 a power supply for driving said semiconductor switching apparatus; and  
 a bypass line disposed in parallel between said first and second electrodes,  
 wherein said bypass includes  
 a capacitive element charged with a main power supply voltage of said power supply at all times.  
 
     
     
       5. The semiconductor switching apparatus of  claim 4 , wherein
 said capacitive element has one end connected direct to said power supply through a resistive of element, and  
 said bypass line further includes  
 a diode having an anode connected to said first electrode and a cathode connected to said one end of said capacitive element.  
 
     
     
       6. The semiconductor switching apparatus of  claim 5 , wherein
 said capacitive element has a capacitance value determined within a limit beyond which a peak voltage between said first and second electrodes developed at said turn-off exceeds said voltage blocking capability of said semiconductor switching element.  
 
     
     
       7. The semiconductor switching apparatus of  claim 1 , wherein said main current is commutated by controlling an inductance existing in a path from said third electrode through said driving control means and said second electrode to said third electrode. 
     
     
       8. A semiconductor switching apparatus comprising:
 a semiconductor switching element having first second and third electrodes for carrying a main current which flows into said first electrode, from said first electrode direct to said second electrode when brought into an on-state in response to a turn-on control current applied to said third electrode; and  
 driving control means connected between said third and second electrodes, for producing said turn-on control current and applying it to said third electrode.  
 wherein said main current is entirely commutated to said driving control means through the first to third electrodes in a direction reverse to said turn-on control current at a turn-off, and  
 wherein a turn-off gain is determined not more than  as 1 at said turn-off, said turn-off gain being represented by the absolute value of the ratio of said main current to a current which flows in said direction reverse to said turn-on control current.  
 
     
     
       9. The semiconductor switching apparatus of  claim 8 , wherein
 an inductance existing in a path from said third electrode through said driving control means and said second electrode to said third electrode is determined a value required to obtain said turn-off gain of not more than  1.  
 
     
     
       10. A semiconductor switching apparatus, comprising:
 a semiconductor switching element; and  
 an interconnection path for transmitting a turn-on control current necessary to turn said semiconductor switching element on to flow into said semiconductor switching element,  
 wherein said interconnection path is disposed so that a main current flowing into said semiconductor switching element in an on-state is entirely commutated to said interconnection path at a turn-off.  
 
     
     
       11. A method of controlling a semiconductor switching element having first, second and third electrodes, comprising steps of:
 providing a driving circuit for generating a turn-on control current for turning on said semiconductor switching element;  
 applying said turn-on control current to said third electrode to bring said semiconductor switching element into an on-state; and  
 commutating a main current flowing into said first electrode entirely towards said second electrode through said driving circuit in a direction reverse to said turn-on control current to turn said semiconductor switching element off.  
 
     
     
       12. The method of  claim 11 , wherein
 said semiconductor switching element is turned off with a turn-off gain which is controlled to be not more than  1, said turn-off gain being represented by the absolute value of the ratio of said main current to a current flowing in said direction reverse to said turn-on control current.  
 
     
     
       13. The method of  claim 12 , further comprising a step of:
 clamping a voltage between said first and second electrodes rising on at a turn-off state to a prescribed voltage value after said semiconductor switching element is brought into said turn-off state, said prescribed voltage value being determined within a limit beyond which said voltage between said first and second electrodes exceeds a voltage blocking capability of said semiconductor switching element.  
 
     
     
       14. The method of  claim 12 , wherein
 said step of providing said driving circuit further comprises a step of  
 providing a capacitive element between said first and second elements, said capacitive element being charged with a power supply voltage of a power supply for driving a semiconductor switching apparatus using said semiconductor switching element at all times, and  
 said method further comprises a step of:  
 bypass-discharging electric charges charged in said capacitive element to a loop including said power supply and said capacitive element in response to a spike voltage and a peak voltage developed with a rise of voltage between said first and second electrodes, after said semiconductor switching element is brought into a turn-off state.  
 
     
     
       15. The semiconductor switching apparatus of  claim 1 , wherein
   no current flows directly between said second electrode and said third electrode during said turn - off during which said main current decreases toward a zero level.     
     
     
       16. The semiconductor switching apparatus of  claim 8 , wherein
   no current flows directly between said second electrode and said third electrode during said turn - off during which said main current decreases toward a zero level.     
     
     
       17. The semiconductor switching apparatus of  claim 10 , wherein
   no current flows directly between said second electrode and said third electrode during said turn - off during which said main current decreases toward a zero level.     
     
     
       18. The method of  claim 11 , wherein
   no current flows directly between said second electrode and said third electrode during said turn - off during which said main current decreases toward a zero level.