Multi-protocol packet framing over an isochronous network

Abstract

An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory. A device residing on a host bus coupled to the integrated circuit may then read the information from the circular ring buffer via a parallel bus port of the integrated circuit. Information may also pass in the opposite direction from the parallel bus port, through a buffer memory port to the buffer memory, and from the buffer memory through the buffer memory port, through an appropriate framer/deframer circuit, through the isochronous network port, and onto the network.

1. An integrated circuit, comprising:
 an isochronous network port;  
 a first protocol packet framer/deframer circuit;  
 a second protocol packet framer/deframer circuit; and  
 a circuit switch multiplexer/demultiplexer coupled to said isochronous network port, said first protocol packet framer/deframer circuit, and said second protocol packet framer/deframer circuit, wherein said circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer, and a storage device, said multiplexer/demultiplexer being at least in part controlled based on a value output from said storage device.  
 
     
     
       2. The integrated circuit of  claim 1 , wherein a plurality of isochronous frames are received on said isochronous network port, each of said isochronous frames comprising a plurality of slots, a first of said slots of a frame being supplied to and deframed by said first protocol packet framer/deframer circuit, a second of said slots of said frame being supplied to and deframed by said second protocol packet framer/deframer circuit. 
     
     
       3. The integrated circuit of  claim 1 , wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots. 
     
     
       4. The integrated circuit of  claim 3 , wherein said first protocol packet framer/deframer circuit deframes ATM cells. 
     
     
       5. The integrated circuit of  claim 3 , wherein said first protocol packet framer/deframer circuit deframes both ATM cells and ATM packets. 
     
     
       6. The integrated circuit of  claim 1 , wherein said storage device comprises a plurality of memory locations, and wherein said circuit switch multiplexer/demultiplexer further comprises:
 a receive counter, said receive counter being incremented after a receipt of a slot of information received on said isochronous network port, a count value output from said receive counter pointing to a corresponding memory location of said plurality of memory locations of said storage device.  
 
     
     
       7. The integrated circuit of  claim 1 , further comprising:
 a parallel bus port, said storage device being accessible from said parallel bus port.  
 
     
     
       8. The integrated circuit of  claim 1 , further comprising:
 a parallel bus port;  
 parallel bus interface circuitry coupled to said parallel bus port;  
 a memory; and  
 an arbiter circuit coupled to said parallel bus interface circuitry and to said memory, said arbiter arbitrating access to said memory.  
 
     
     
       9. The integrated circuit of  claim 8 , further comprising:
 a buffer manager circuit coupled to said first protocol packet framer/deframer circuit, said second protocol packet framer/deframer circuit and to said arbiter circuit, said buffer manager circuit comprising: 
 first and second receive pointer registers for pointing to a receive buffer in said memory; and  
 first and second transmit pointer registers for pointing to a transmit buffer in said memory.  
 
 
     
     
       10. The integrated circuit of  claim 8 , further comprising:
 means, coupled to said circuit switch multiplexer/demultiplexer, for managing buffering of substantially nondeframed isochronous network data in said memory.  
 
     
     
       11. A method, comprising:
 deframing information of a slot of a frame of network information using a first protocol packet deframer circuit;  
 deframing information of another slot of said frame of network information using a second protocol packet deframer circuit, said first and second protocol packet deframer circuits both being disposed on the same integrated circuit;  
 incrementing a counter of said integrated circuit so that a count value output from said counter corresponds with a slot number of the slot being received into said integrated circuit; and  
 using said count value to address a slot mapping memory of said integrated circuit.  
 
     
     
       12. The method of  claim 11 , wherein said integrated circuit has a parallel bus port, said method further comprising:
 programming said slot mapping memory of said integrated circuit via said parallel bus port.  
 
     
     
       13. The method of  claim 11 , further comprising:
 storing information deframed by said first protocol packet deframer circuit in a first ring buffer; and  
 storing information deframed by said second protocol packet deframer circuit in a second ring buffer.  
 
     
     
       14. An integrated circuit, comprising:
 a first packet deframer circuit which deframes information in accordance with a first network protocol;  
 a second packet deframer circuit which deframes information in accordance with a second network protocol; and  
 means for causing said first packet deframer circuit to deframe information in a first isochronous network slot of a frame in accordance with said first network protocol and for causing said second packet deframer circuit to deframe information in a second isochronous network slot of said frame in accordance with said second network protocol, wherein said means comprises means for storing slot mapping information.  
 
     
     
       15. The integrated circuit of  claim 14 , wherein said first network protocol is an ATM protocol and wherein said second network protocol is an HDLC protocol. 
     
     
       16. An integrated circuit comprising:
 a first packet deframer circuit which deframes information in accordance with a first network protocol;  
 a second packet deframer circuit which deframes information in accordance with a second network protocol;  
 means for causing said first packet deframer circuit to deframe information in a first isochronous network slot of a frame in accordance with said first network protocol and for causing said second packet deframer circuit to deframe information in a second isochronous network slot of said frame in accordance with said second network protocol;  
 means for managing a receive ring buffer;  
 a parallel bus port; and  
 parallel bus interface circuitry coupled to said parallel bus port.  
 
     
     
       17. The integrated circuit of  claim 14 , further comprising:
 a first packet framer circuit which frames information in accordance with a network protocol; and  
 a second packet framer circuit which frames information in accordance with a network protocol,  
 wherein said means for causing comprises: 
 a multiplexer having a first input lead, a second input lead, and an output lead, said first input lead being coupled to an output lead of said first packet framer circuit, said second input lead being coupled to an output lead of said second packet framer circuit, and an output lead being coupled to an output part of an isochronous network port of said integrated circuit; and  
 a demultiplexer having an input lead, a first output lead, and a second output lead, said input lead being coupled to an input part of said isochronous network port, said first output lead being coupled to an input lead of said first packet deframer circuit, and said second output lead being coupled to an input lead of said second packet deframer circuit.  
 
 
     
     
       18. An integrated circuit, comprising:
 an isochronous network port, wherein the isochronous network port receives frame of information, said frame having a plurality of non-isochronous and isochronous slots, and each of said isochronous slots having information of one of at least a first protocol or a second protocol;  
 a first protocol packet framer/deframer circuit;  
 a second protocol packet framer/deframer circuit; and  
 a circuit switch multiplexer/demultiplexer coupled to said isochronous network port, said first protocol packet framer/deframer circuit, and said second protocol packet framer/deframer circuit, wherein the circuit switch multiplexer/demultiplexer couples said isochronous first protocol slots to the first protocol packet framer/deframer circuit and couples said isochronous second protocol slots to the second protocol packet framer/deframer circuit.  
 
     
     
       19. The integrated circuit of  claim 18  further comprising:
 a first demultiplexer coupled to said isochronous network port, wherein the first demultiplexer separates the non-isochronous slots from the isochronous slots, and the circuit switch multiplexer/demultiplexer is coupled to the first demultiplexer.  
 
     
     
       20. The integrated circuit of  claim 18 , wherein said circuit switch multiplexer/demultiplexer comprises:
 a multiplexer/demultiplexer; and  
 a storage device, said multiplexer/demultiplexer being at least in part controlled based on a value output from said storage device.  
 
     
     
       21. The integrated circuit of  claim 18 , wherein a plurality of isochronous slots are received on said isochronous network port, a first of said isochronous slots of a frame being provided to and deframed by said first protocol packet framer/deframer circuit, and a second of said isochronous slots of said frame being provided to and deframed by said second protocol packet framer/deframer circuit. 
     
     
       22. The integrated circuit of  claim 18 , wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots. 
     
     
       23. The integrated circuit of  claim 22 , wherein said first protocol packet framer/deframer circuit deframes ATM cells. 
     
     
       24. The integrated circuit of  claim 22 , wherein said first protocol packet framer/deframer circuit deframes both ATM cells and ATM packets. 
     
     
       25. The integrated circuit of  claim 20 , wherein said storage device comprises a plurality of memory locations, and wherein said circuit switch multiplexer/demultiplexer further comprises:
 a receive counter, said receive counter being incremented after a receipt of a slot of information received on said isochronous network port, a count value output from said receive counter pointing to a corresponding memory location of said plurality of memory locations of said storage device.  
 
     
     
       26. The integrated circuit of  claim 20 , further comprising:
 a parallel bus port, said storage device being accessible from said parallel bus port.  
 
     
     
       27. The integrated circuit of  claim 20 , further comprising:
 a parallel bus port;  
 parallel bus interface circuitry coupled to said parallel bus port;  
 a memory; and  
 an arbiter circuit coupled to said parallel bus interface circuitry and to said memory, said arbiter arbitrating access to said memory.  
 
     
     
       28. The integrated circuit of  claim 27 , further comprising:
 a buffer manager circuit coupled to said first protocol packet framer/deframer circuit, said second protocol packet framer/deframer circuit and to said arbiter circuit, said buffer manager circuit comprising:  
 first and second receive pointer registers for pointing to a receive buffer in said memory; and  
 first and second transmit pointer registers for pointing to a transmit buffer in said memory.  
 
     
     
       29. The integrated circuit of  claim 27 , further comprising:
 means, coupled to said circuit switch multiplexer/demultiplexer, for managing buffering of substantially nondeframed isochronous network data in said memory.  
 
     
     
       30. A method, comprising:
 framing network information, wherein network information frames include non-isochronous and isochronous slots;  
 deframing information of an isochronous slot of using a first protocol packet deframer circuit; and  
 deframing information of another isochronous slot using a second protocol packet deframer circuit, said first and second protocol packet deframer circuits both being disposed on the same integrated circuit.  
 
     
     
       31. The integrated circuit of  claim 30 , wherein said first protocol packet framer/deframer circuit deframes ATM formatted slots, and wherein said second protocol packet framer/deframer circuit deframes HDLC formatted slots. 
     
     
       32. The method of  claim 30  wherein each isochronous slot is formatted with at least one of a first protocol or a second protocol, the method further comprising the steps of:
 separating the non-isochronous slots from the isochronous slots into a non-isochronous data stream and an isochronous data stream;  
 coupling the isochronous slots formatted with the first protocol to the first protocol packet deframer circuit; and  
 coupling the isochronous slots formatted with the second protocol to the second protocol packet deframer circuit.  
 
     
     
       33. The method of  claim 32  further comprising the step of:
 demultiplexing the isochronous slots; and  
 wherein the separating step includes the step of demultiplexing with a first demultiplexer each network information frame.  
 
     
     
       34. The method of  claim 30  further comprising the steps of:
 flaming information having a first protocol using a first protocol packet framer circuit;  
 framing information having a second protocol using a second protocol packet framer circuit;  
 combining the first protocol framed information and the second protocol framed information into isochronous slots; and  
 combining isochronous slots with non-isochronous slots into a frame.  
 
     
     
       35. The method of  claim 30 , further comprising:
 incrementing a counter of said integrated circuit so that a count value output from said counter corresponds with a slot number of the slot being received into said integrated circuit; and using said count value to address a slot mapping memory of said integrated circuit.  
 
     
     
       36. The method of  claim 35 , wherein said integrated circuit has a parallel bus port, said method further comprising:
 programming said slot mapping memory of said integrated circuit via said parallel bus port.  
 
     
     
       37. The method of  claim 35 , further comprising:
 storing information deframed by said first protocol packet deframer circuit in a first ring buffer; and  
 storing information deframed by said second protocol packet deframer circuit in a second ring buffer.  
 
     
     
       38. An integrated circuit, comprising:
 means for framing information, each information frame having isochronous and non-isochronous slots and each of said isochronous slots having information formatted by one of at least a first network protocol or a second network protocol;  
 means for receiving the framed information;  
 means for separating the isochronous slots and the non-isochronous slots;  
 a first means for combining information formatted by a first protocol into a first packet;  
 a second means for combining information formatted by a second protocol into a second packet; and  
 means for coupling first protocol formatted information in an isochronous slot to the first means for combining and for coupling second protocol formatted information in another isochronous slot to the second means for combining.  
 
     
     
       39. The integrated circuit of  claim 38  further comprising:
 a first means for separating a packet of information formatted by a first protocol into first segments of information;  
 a second means for disassembling a packet of information formatted by a second protocol into second segments of information; and  
 means for combining the first information segments and the second information segments into an isochronous data stream; means for combining the isochronous data stream with a non-isochronous data stream.  
 
     
     
       40. The integrated circuit as in  claim 39  wherein the means for combining includes the step of inserting the first segments and the second segments into isochronous slots of a frame and non-isochronous data stream segments into non-isochronous slots of the frame. 
     
     
       41. The integrated circuit of  claim 38 , wherein said first network protocol is an ATM protocol and wherein said second network protocol is an HDLC protocol. 
     
     
       42. The integrated circuit of  claim 38 , wherein said means for coupling comprises means for storing slot mapping information. 
     
     
       43. The integrated circuit of  claim 38 , further comprising:
 means for managing a receive ring buffer;  
 a parallel bus port; and  
 parallel bus interface circuitry coupled to said parallel bus port.  
 
     
     
       44. The integrated circuit of  claim 38 , further comprising:
 a first packet framer circuit which frames information in accordance with a network protocol; and  
 a second packet framer circuit which frames information in accordance with a network protocol,  
 wherein said means for coupling comprises: a multiplexer having a first input lead, a second input lead, and an output lead, said first input lead being coupled to an output lead of said first packet framer circuit, said second input lead being coupled to an output lead of said second packet framer circuit, and an output lead being coupled to an output part of an isochronous network port of said integrated circuit; and  
 a demultiplexer having an input lead, a first output lead, and a second output lead, said input lead being coupled to an input part of said isochronous network port, said first output lead being coupled to an input lead of said first packet deframer circuit, and said second output lead being coupled to an input lead of said second packet deframer circuit.  
 
     
     
       45. An apparatus, comprising:
   an isochronous port;        one or more first protocol packet framer/deframer circuits;        one or more second protocol packet framer/deframer circuits; and        a circuit switch multiplexer/demultiplexer coupled to the isochronous port, at least one of the first protocol packet framer/deframer circuits, and at least one of the second protocol packet framer/deframer circuits, wherein the circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer and a storage device, the multiplexer/demultiplexer being at least in part controlled based on an output from the storage device.      
     
     
       46. The apparatus of  claim 45 , wherein the isochronous port comprises a time division multiplexed port.  
     
     
       47. An apparatus, comprising:
   an isochronous port;        a first protocol circuit;        a second protocol circuit; and        a circuit switch multiplexer/demultiplexer coupled to the isochronous port, the first protocol circuit, and the second protocol circuit, wherein the circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer and a storage device, the multiplexer/demultiplexer being at least in part controlled based on an output from the storage device.      
     
     
       48. The apparatus of  claim 47 , wherein the first protocol circuit manages raw data.  
     
     
       49. The apparatus of  claim 47 , wherein the first protocol circuit manages unframed data.  
     
     
       50. The apparatus of  claim 47 , wherein the first protocol circuit manages nondeframed data.  
     
     
       51. The apparatus of  claim 47 , wherein the first protocol circuit comprises a constant bit rate buffer circuit.  
     
     
       52. The apparatus of  claim 47 , wherein the second protocol circuit comprises a packet framer/deframer circuit.  
     
     
       53. The apparatus of  claim 47 , wherein the second protocol circuit comprises an HDLC framer/deframer circuit.  
     
     
       54. The apparatus of  claim 47 , wherein the second protocol circuit comprises multiple packet framer/deframer circuits.  
     
     
       55. The apparatus of  claim 47 , wherein the second protocol circuit comprises multiple HDLC framer/deframer circuits.  
     
     
       56. The apparatus of  claim 47 , wherein the second protocol circuit comprises an asynchronous transfer mode framer/deframer circuit.  
     
     
       57. The apparatus of  claim 47 , wherein the isochronous port comprises a time division multiplexed port.  
     
     
       58. An apparatus, comprising:
   an isochronous port;        one or more first protocol circuits;        one or more second protocol circuits;        a circuit switch multiplexer/demultiplexer coupled to the isochronous port, at least one of the first protocol circuits, and at least one of the second protocol circuits, wherein the circuit switch multiplexer/demultiplexer comprises a multiplexer/demultiplexer and a storage device, the multiplexer/demultiplexer being at least in part controlled based on an output from the storage device; and        a buffer memory, wherein a signal path is provided from the isochronous port to at least one of the first protocol circuits, and from the at least one first protocol circuit to the buffer memory, and from the buffer memory to at least one of the second protocol circuits, and from the second protocol circuit to the isochronous port.      
     
     
       59. The apparatus of  claim 58 , wherein at least one of the first protocol circuit manages raw data.  
     
     
       60. The apparatus of  claim 58 , wherein at least one of the first protocol circuit manages unframed data.  
     
     
       61. The apparatus of  claim 58 , wherein the first protocol circuit manages nondeframed data.  
     
     
       62. The apparatus of  claim 58 , wherein the first protocol circuit comprises a constant bit rate buffer circuit.  
     
     
       63. The apparatus of  claim 58 , wherein the second protocol circuit comprises a packet framer/deframer circuit.  
     
     
       64. The apparatus of  claim 58 , wherein the second protocol circuit comprises an HDLC framer/deframer circuit.  
     
     
       65. The apparatus of  claim 58 , wherein the second protocol circuit comprises multiple packet framer/deframer circuits.  
     
     
       66. The apparatus of  claim 58 , wherein the second protocol circuit comprises multiple HDLC framer/deframer circuits.  
     
     
       67. The apparatus of  claim 58 , wherein the second protocol circuit comprises an asynchronous transfer mode framer/deframer circuit.  
     
     
       68. The apparatus of  claim 58 , wherein the isochronous port comprises a time division multiplexed port.  
     
     
       69. A method, comprising:
   deframing information of a received slot of information using a first protocol packet deframer circuit;        deframing information of another received slot of information using a second protocol packet deframer circuit;        generating an output that corresponds with the slot being received; and        using the output to address a slot mapping memory.      
     
     
       70. An apparatus, comprising:
   a first packet deframer circuit which deframes information in accordance with a first protocol;        a second packet deframer circuit which deframes information in accordance with a second protocol; and        means for causing the first packet deframer circuit to deframe information in a first isochronous slot of a frame in accordance with the first protocol and for causing the second packet deframer circuit to deframe information in a second isochronous slot of the frame in accordance with the second protocol, wherein the means comprises means for storing slot mapping information.      
     
     
       71. An apparatus comprising:
   a first packet deframer circuit which deframes information in accordance with a first protocol;        a second packet deframer circuit which deframes information in accordance with a second protocol;        means for causing the first packet deframer circuit to deframe information in a first isochronous slot of a frame in accordance with the first protocol and for causing the second packet deframer circuit to deframe information in a second isochronous slot of the frame in accordance with the second protocol;        means for managing a receive buffer;        a port; and        interface circuitry coupled to the port.      
     
     
       72. An apparatus comprising:
   a first packet deframer circuit which deframes information in accordance with a first protocol;        a second packet deframer circuit which deframes information in accordance with a second protocol;        means for causing the first packet deframer circuit to deframe information in a first isochronous slot of a frame in accordance with the first network protocol and for causing the second packet deframer circuit to deframe information in a second isochronous slot of the frame in accordance with the second protocol;        means for managing a receive buffer;        a bus port for coupling to a bus; and        interface circuitry coupled to the bus port, wherein the bus supports multiple transfer types, such as direct memory access, shared memory access or standard I/O access.      
     
     
       73. An apparatus, comprising:
   an isochronous port, wherein the isochronous port receives a frame of information, the frame having a plurality of non - isochronous and isochronous slots, and each of the isochronous slots having information of one of at least a first protocol or a second protocol;        a first protocol packet framer/deframer circuit;        a second protocol packet framer/deframer circuit; and        a circuit switch multiplexer/demultiplexer coupled to the isochronous port, the first protocol packet framer/deframer circuit, and the second protocol packet framer/deframer circuit, wherein the circuit switch multiplexer/demultiplexer couples the isochronous first protocol slots to the first protocol packet framer/deframer circuit and couples the isochronous second protocol slots to the second protocol packet framer/deframer circuit.      
     
     
       74. A method, comprising:
   framing information, wherein information frames include non - isochronous and isochronous slots;        deframing information of an isochronous slot of using a first protocol packet deframer circuit; and        deframing information of another isochronous slot using a second protocol packet deframer circuit, said first and second protocol packet deframer circuits being coupled to a common buffer memory.      
     
     
       75. An apparatus, comprising:
   means for framing information, each information frame having isochronous and non - isochronous slots and each of the isochronous slots having information formatted by one of at least a first protocol or a second protocol;        means for receiving the framed information;        means for separating the isochronous slots and the non - isochronous slots;        a first means for combining information formatted by a first protocol into a first packet;        a second means for combining information formatted by a second protocol into a second packet; and        means for coupling first protocol formatted information in an isochronous slot to the first means for combining and for coupling second protocol formatted information in another isochronous slot to the second means for combining.      
     
     
       76. An apparatus comprising:
   a network port;        a multiplexer/demultiplexer circuit coupled to the network port;        a first protocol circuit and a second protocol circuit each coupled to the multiplexer/demultiplexer circuit; and        a buffer coupled to the first and second protocol circuit;        wherein a signal path is provided from the network port to the first protocol circuit, and from the first protocol circuit to the buffer, and from the buffer to the second protocol circuit, and from the second protocol circuit to the network port.      
     
     
       77. The apparatus of  claim 76 , wherein the first protocol circuit manages raw data.  
     
     
       78. The apparatus of  claim 76 , wherein the first protocol circuit manages unframed data.  
     
     
       79. The apparatus of  claim 76 , wherein the first protocol circuit manages nondeframed data.  
     
     
       80. The apparatus of  claim 76 , wherein the first protocol circuit comprises a constant bit rate buffer circuit.  
     
     
       81. The apparatus of  claim 76 , wherein the second protocol circuit comprises a packet framer/deframer circuit.  
     
     
       82. The apparatus of  claim 76 , wherein the second protocol circuit comprises an HDLC framer/deframer circuit.  
     
     
       83. The apparatus of  claim 76 , wherein the second protocol circuit comprises multiple packet framer/deframer circuits.  
     
     
       84. The apparatus of  claim 76 , wherein the second protocol circuit comprises multiple HDLC framer/deframer circuits.  
     
     
       85. The apparatus of  claim 76 , wherein the second protocol circuit comprises an asynchronous transfer mode framer/deframer circuit.  
     
     
       86. The apparatus of  claim 76 , wherein the network port comprises a time division multiplexed port.  
     
     
       87. A method comprising:
   coupling information from a network to an isochronous port, the information including non - isochronous and isochronous slots;        coupling the information from the isochronous port to a multiplexer/demultiplexer;        selectively coupling the information from the multiplexer/demultiplexer to a first protocol circuit and a second protocol circuit; and        selectively coupling the information from/to the first and second protocol circuit to a buffer;        wherein a signal path is provided from the isochronous port to the first protocol circuit, and from the first protocol circuit to the buffer, and from the buffer to the second protocol circuit, and from the second protocol circuit to the isochronous port.      
     
     
       88. The method of  claim 87 , wherein the first protocol circuit manages raw data.  
     
     
       89. The method of  claim 87 , wherein the first protocol circuit manages unframed data.  
     
     
       90. The method of  claim 87 , wherein the first protocol circuit manages nondeframed data.  
     
     
       91. The method of  claim 87 , wherein the first protocol circuit comprises a constant bit rate buffer circuit.  
     
     
       92. The method of  claim 87 , wherein the second protocol circuit comprises a packet framer/deframer circuit.  
     
     
       93. The method of  claim 87 , wherein the second protocol circuit comprises an HDLC framer/deframer circuit.  
     
     
       94. The method of  claim 87 , wherein the second protocol circuit comprises multiple packet framer/deframer circuits.  
     
     
       95. The method of  claim 87 , wherein the second protocol circuit comprises multiple HDLC framer/deframer circuits.  
     
     
       96. The method of  claim 87 , wherein the second protocol circuit comprises an asynchronous transfer mode framer/deframer circuit.  
     
     
       97. The method of  claim 87 , wherein the network port comprises a time division multiplexed port.