Semiconductor device

Abstract

The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.

1. A semiconductor device circuit comprising:
 a first MISFET of an n-type which is connected between a node of a signal transmission line and a low-potential source and uses a poly-crystalline silicon layer as an active region, the first MISFET having a poor saturation characteristic, due to use of the poly-crystalline silicon and the n-type, in which an increase in drain current does not saturate with an increase in drain voltage within an operating range;  
 a second MISFET of the n-type which is connected between the node and the first MISFET and uses a poly-crystalline silicon layer as an active region, the second MISFET having a poor saturation characteristic, due to use of poly-crystalline silicon and the n-type, in which an increase in drain current does not saturate with an increase in drain voltage within an operating range, and the second MISFET being configured to suppress variations in voltage at the node caused by poor saturation characteristic of the first MISFET; and  
 a first bias circuit portion configured to apply a first bias voltage to a gate of the second MISFET,  
 wherein a combination of the first and second MISFETs and the first bias circuit portion is arranged to function as an alternative to one MISFET of the n-type using a single-crystalline silicon layer as an active region; and  
   wherein the poly - crystalline silicon layers are disposed, through an insulating film, on a single - crystalline semiconductor layer in which a main semiconductor switch is formed.    
 
     
     
       2. A circuit according to  claim 1 , further comprising:
 a third MISFET of the n-type which is connected to the low-potential source in parallel with the second first MISFET and uses a poly-crystalline silicon layer as an active region, the third MISFET having a poor saturation characteristic, due to use of the poly-crystalline silicon and the n-type, in which an increase in drain current does not saturate with an increase in drain voltage within an operating range;  
 a fourth MISFET of the n-type which is series-connected to a drain of the third MISFET and uses a poly-crystalline silicon layer as an active region, the fourth MISFET having a poor saturation characteristic, due to use of the poly crystalline silicon and the n-type, in which an increase in drain current does not saturate with an increase in drain voltage within an operating range, and the fourth MISFET being configured to suppress variations in voltage at the node caused by the poor saturation characteristic of the third MISFET;  
 a second bias current portion configured to apply a said first bias voltage to a gate of the fourth MISFET; and  
 first and second input circuit portions configured to input differential signals to gates of the first and third MISFETs, respectively,  
 wherein a combination of the third and fourth MISFETs and the second bias circuit portion is arranged to function as an alternative to one MISFET of the n-type using a single-crystalline silicon layer as an active region.  
 
     
     
       3. A circuit according to  claim 2 , wherein the first to fourth MISFETs, the first and second bias current portions, and the first and second input circuit portions are part of a differential amplifier. 
     
     
       4. A circuit according to  claim 2 , further comprising:
 a fifth MISFET of the n-type which is connected between an output terminal and a the low-potential source and uses a poly-crystalline silicon layer as an active region, the fifth MISFET having a poor saturation characteristic, due to use of the poly-crystalline silicon and the n-type, in which an increase in drain current does not saturate with an increase in drain voltage within an operating range;  
 a sixth MISFET of the n-type which is connected between the output terminal and the fifth MISFET and uses a poly-crystalline silicon layer as an active region, the sixth MISFET having a poor saturation characteristic, due to use of the poly-crystalline silicon and the n-type, in which an increase in drain current does not saturate with an increase in drain voltage within an operating range, and the sixth MISFET being configured to suppress variations in voltage at the node caused by the poor saturation characteristic of the fifth MISFET;  
 a third bias circuit portion configured to apply a bias voltage to a gate of the fifth MISFET; and  
 a fourth bias current portion configured to apply a bias voltage to a gate of the sixth MISFET,  
 wherein a combination of the fifth and sixth MISFETs and the fourth bias circuit portion is arranged to function as an alternative to one MISFET of the n-type using a single-crystalline silicon layer as an active region.  
 
     
     
       5. A circuit according to  claim 4 , wherein the fifth and sixth MISFETs and the third and fourth bias circuit portions are part of a current source circuit. 
     
     
       6. A circuit according to  claim 4 , wherein the first to fourth MISFETs, the first and second bias circuit portions, and the first and second input circuit portions are part of a differential amplifier, the fifth and sixth MISFETs and the third and fourth bias circuit portions are of a current source circuit, and the differential amplifier and the current source circuit are part of a comparator. 
     
     
       7. A circuit according to  claim 1 , wherein the poly-crystalline silicon layers are disposed, through an insulating film, on a single-crystalline semiconductor layer in which a main semiconductor switch is formed. 
     
     
       8. A circuit according to claim  7   1 , wherein the circuit is part of a semiconductor protection device configured to protect the main semiconductor switch. 
     
     
       9. A circuit, comprising:
 a differential amplifier connected to an output stage, wherein each of said differential amplifier and said output stage comprises:  
 a first n-type MISFET connected in series with a second n-type MISFET, each of said first and second MISFETs having a poly-crystalline silicon layer as an active region; and  
 a bias circuit portion configured to apply a bias voltage to a gate of each of the first MISFETs,  
   a current capability of said first MISFET of said output stage being greater than a current capability of said second MISFET of said output stage.    
 
     
     
       10. A circuit according to  claim 9 , comprising:
 said first MISFET connected directly in series with said second MISFET.  
 
     
     
       11. A circuit according to  claim 9 , comprising:
 said first MISFET and said second MISFET of said differential amplifier being connected between a first node and a low level potential source, said first MISFET of said differential amplifier being configured to suppress voltage variations at said first node; and  
 said first MISFET and said second MISFET of said output stage being connected together at a second node, said first MISFET of said output stage being configured to suppress voltage variations at said second node.  
 
     
     
       12. A circuit according to  claim 11 , comprising:
 a current capability of said first MISFET of said output stage being greater than a current capability of said second MISFET of said output stage.    
     
     
       13. A circuit according to  claim 9 , comprising:
 a current capability of said first MISFET of said output stage being greater than a current capability of said second MISFET of said output stage.    
     
     
       14. A circuit according to  claim 9 , comprising:
 said first MISFET series-connected to a drain of said second MISFET.  
 
     
     
       15. The circuit according to  claim 1 , further comprising a circuit portion configured to apply a bias voltage to a gate of the first MISFET, wherein the circuit constitutes a current source circuit. 
     
     
       16. The circuit according to  claim 1 , further comprising:
 a third n-type MISFET which is connected to the low-potential source in parallel with the first MISFET and uses a semiconductor layer as an active region;  
 a fourth n-type MISFET which is series-connected to a drain of the third MISFET and uses a semiconductor layer as an active region;  
 a first circuit portion configured to connect a gate of the first MISFET to a gate and the drain of the third MISFET; and  
 a second circuit portion configured to apply a bias voltage to a gate of the fourth MISFET,  
 wherein the circuit constitutes a current mirror circuit of a differential amplifier.  
 
     
     
       17. The circuit according to  claim 1 , further comprising:
 a third p-type MISFET which is connected between the node and a high-potential source and uses a semiconductor layer as an active region; and  
 an input circuit portion configured to input a logic signal to gates of the first and third MISFETs,  
 wherein the circuit constitutes a CMOS logic gate circuit arranged such that a logic signal is output from the node.  
 
     
     
       18. The circuit according to  claim 17  wherein the third MISFET has a poor saturation characteristic in which an increase in drain current does not saturate with an increase in drain voltage within an operating range,
 the circuit further comprising: 
 a fourth p-type MISFET which is connected between the node and the third MISFET and uses a semiconductor layer as an active region, the fourth MISFET being configured to suppress variations in voltage at the node caused by the poor saturation characteristic of the third MISFET; and  
 a circuit portion configured to apply a bias voltage to a gate of the fourth MISFET.  
 
 
     
     
       19. The circuit according to  claim 1 , further comprising:
 a p-type main MISFET which is connected between the node and a high-potential source and uses a semiconductor layer as an active region, the main MISFET having a poor saturation characteristic in which an increase in drain current does not saturate with an increase in drain voltage within an operating range;  
 a p-type sub-MISFET which is connected between the node and the main MISFET and uses a semiconductor layer as an active region, the sub-MISFET being configured to suppress variations in voltage at the node caused by the poor saturation characteristic of the main MISFET; and  
 a circuit portion configured to apply a bias voltage to a gate of the sub-MISFET.  
 
     
     
       20. A semiconductor device circuit comprising:
   a switching device having a control terminal and connected between an input terminal of a main switching device and a low - potential source;        a first MISFET of an n - type which is connected between a first node connected to said control terminal and a low - potential source and uses a poly - crystalline silicon layer as an active region;        a second MISFET of the n - type which is connected between the first node and the first MISFET and uses a poly - crystalline silicon layer as an active region; and        a first bias circuit portion configured to apply a bias voltage to a gate of the second MISFET; and        said second MISFET having a greater current capability than said first MISFET.     
     
     
       21. The device according to  claim 20 , comprising:
   each of said first and second MISFETs having a poor saturation characteristic; and        said second MISFET being configured to suppress variations in voltage at the node caused by the poor saturation characteristic of the first MISFET.     
     
     
       22. The device according to  claim 20 , comprising:
   said first MISFET and said second MISFET being connected together at a second node;        said second MISFET being configured to suppress variations in voltage at said second node.     
     
     
       23. The device according to  claim 20 , comprising:
   said main switching device being formed in a single crystal silicon material; and        said poly - crystalline silicon layers of said first and second MISFETs being disposed on said single crystal silicon layer with an insulating film being disposed between said poly - crystalline layers and said single crystal silicon material.     
     
     
       24. A semiconductor device circuit comprising:
   a switching device having a control terminal and connected between an input terminal of a main switching device and a low - potential source;        a sense circuit having an output connected to said control terminal, said sense circuit comprising:      a first MISFET of an n - type which is connected between a node and a low - potential source and uses a poly - crystalline silicon layer as an active region;        a second MISFET of the n - type which is connected between the node and the first MISFET and uses a poly - crystalline silicon layer as an active region; and        a first bias circuit portion configured to apply a bias voltage to a gate of the second MISFET,        said second MISFET having a greater current capability than said first MISFET.       
     
     
       25. The device according to  claim 24 , wherein a combination of the first and second MISFETs and the first bias circuit portion is arranged to function as an alternative to one MISFET of the n- type using a single - crystalline silicon layer as an active region.   
     
     
       26. The device according to  claim 24 , further comprising:
   a third MISFET of the n - type which is connected to the low - potential source in parallel with the first MISFET and uses a poly - crystalline silicon layer as an active region;        a fourth MISFET of the n - type which is series - connected to a drain of the third MISFET and uses a poly - crystalline silicon layer as an active region; and        a second bias circuit portion configured to apply a bias voltage to a gate of the fourth MISFET; and        first and second input circuit portions configured to input differential signals to gates of the first and third MISFETs, respectively.     
     
     
       27. The device according to  claim 26 , wherein a combination of the third and fourth MISFETs and the second bias circuit portion is arranged to function as an alternative to one MISFET of the n- type using a single - crystalline silicon layer as an active region.   
     
     
       28. The device according to  claim 26 , wherein the fourth MISFET is configured to suppress variations in voltage at the node caused by the poor saturation characteristic of the third MISFET. 
     
     
       29. The device according to  claim 26 , wherein the first to fourth MISFETs, the first and second bias circuit portions, and the first and second input circuit portions are part of a differential amplifier. 
     
     
       30. The device according to  claim 26 , further comprising:
   a fifth MISFET of the n - type which is connected between an output terminal and the low - potential source and uses a poly - crystalline silicon layer as an active region;        a sixth MISFET of the n - type which is connected between the output terminal and the fifth MISFET and uses a poly - crystalline silicon layer as an active region        a third bias circuit portion configured to apply a bias voltage to a gate of the fifth MISFET; and        a fourth bias current portion configured to apply a bias voltage to a gate of the sixth MISFET.     
     
     
       31. The device according to  claim 30 , wherein the sixth MISFET is configured to suppress variations in voltage at a node between said fifth and sixth MISFETs caused by poor saturation characteristic of the fifth MISFET. 
     
     
       32. The device according to  claim 30 , wherein a combination of the fifth and sixth MISFETs and the fourth bias circuit portion is arranged to function as an alternative to one MISFET of the n- type using a single - crystalline silicon layer as an active region.   
     
     
       33. The device according to  claim 24 , wherein the fifth and sixth MISFETs and the third and fourth bias circuit portions are part of a current source circuit. 
     
     
       34. The device according to  claim 24 , wherein the first and second MISFETs and the first bias circuit portion are part of a current source circuit. 
     
     
       35. The device according to  claim 24 , wherein:
   said main switching device being formed in a single crystal silicon material; and        said poly - crystalline silicon layers of said first and second MISFETs being disposed on said single crystal silicon layer with an insulating film being disposed between said poly - crystalline layers and said single crystal silicon material.     
     
     
       36. The device according to  claim 24 , comprising:
   said main switching device having a sense terminal; and        said sense circuit being connected between said sense terminal and said control terminal.     
     
     
       37. The device according to  claim 24 , comprising:
   said sense circuit being configured to control said control terminal based upon a sense current flowing into said sense circuit exceeding a predetermined value.     
     
     
       38. The device according to  claim 24 , comprising:
   said sense circuit being configured to control said control terminal based upon a sense current flowing into said sense circuit to decrease a voltage applied to a main control electrode of said main switching device.     
     
     
       39. The device according to  claim 38 , comprising:
   said sense circuit being configured to control said control terminal based upon a sense current flowing into said sense circuit exceeding a predetermined value.     
     
     
       40. A semiconductor device circuit comprising:
   a switching device having a control terminal and connected between an input terminal of a main switching device and a low - potential source;        a first MISFET of an n - type which is connected between a first node connected to said control terminal and a low - potential source and uses a poly - crystalline silicon layer as an active region;        a second MISFET of the n - type which is connected between the first node and the first MISFET and uses a poly - crystalline silicon layer as an active region; and        a first bias circuit portion configured to apply a bias voltage to a gate of the second MISFET,        said main switching device being formed in a single crystal silicon material; and        said poly - crystalline silicon layers of said first and second MISFETs being diposed on said single crystal silicon layer with an insulating film being disposed between said poly - crystalline layers and said single crystal silicon material.     
     
     
       41. A semiconductor device circuit comprising:
   a switching device having a control terminal and connected between an input terminal of a main switching device and a low - potential source;        a sense circuit having an output connected to said control terminal, said sense circuit comprising:        a first MISFET of an n - type which is connected between a node and a low - potential source and uses a poly - crystalline silicon layer as an active region;        a second MISFET of the n - type which is connected between the node and the first MISFET and uses a poly - crystalline silicon layer as an active region; and        a first bias circuit portion configured to apply a bias voltage to a gate of the second MISFET,        said main switching device being formed in a single crystal silicon material; and        said poly - crystalline silicon layers of said first and second MISFETs being disposed on said single crystal silicon layer with an insulating film being disposed between said poly - crystalline layers and said single crystal silicon material.