Memory device having a relatively wide data bus

Abstract

An architecture for a wide data path in a memory device formed in a semiconductor substrate includes an array of memory cells is formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns. A plurality of complementary pairs of digit lines are formed in the array region from a first conductive layer, each complementary pair being coupled to a plurality of memory cells in an associated column. A plurality of word lines are formed in the array region from a second conductive layer, each word line being coupled to each memory cell in an associated row. A plurality of sense amplifiers are formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier being coupled to an associated pair of complementary digit lines. A plurality of input/output lines are disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers. At least one column select line is disposed in a portion of the third conductive layer formed above the sense-amplifier region, each column select line being coupled to at least some of the sense amplifiers. The memory device also includes a row address decoder, column address decoder, data path circuit, and control circuit that operate in response to signals applied on respective busses to transfer data to and from the memory device. The architecture may be used, for example, in packetized DRAMs, such as SLDRAMs, and in Embedded DRAMs.

1. A memory-cell array formed in a semiconductor substrate, comprising:
 a plurality of memory cells arranged in rows and columns. , the memory cells formed in an array region of the substrate;  
 a plurality of complementary pairs of digit lines formed in the array region. , each complementary pair coupled to a plurality of memory cells in an associated column;  
 a plurality of word lines formed in the array region, each word line coupled to each memory cell in an associated row;  
 a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines;  
 a plurality of input/output lines formed above the array region, each input/output line coupled to at least a pair of the sense amplifiers through a respective switch;  
 and at least one column select line formed above the sense amplifier region, each column select line coupled to a control input of a plurality of the switches of respective sense amplifiers.  
 
     
     
       2. The memory-cell array of  claim 1  wherein each switch includes an NMOS transistor. 
     
     
       3. The memory-cell array of  claim 1  wherein the memory-cell array includes 512 input/output lines and two column select lines. 
     
     
       4. The memory-cell array of  claim 1  wherein each switch is coupled to first and second column select lines, and couples an associated data line to one of two associated sense amplifiers responsive to respective column select signals received on the first and second column lines. 
     
     
       5. The memory-cell array of  claim 1  wherein the input/output lines are formed substantially parallel to the digit lines and the column select lines are substantially perpendicular to the digit lines. 
     
     
       6. A memory-cell array formed in a semiconductor substrate, comprising:
 an array of memory cells formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns;  
 a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row;  
 a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column;  
 a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines;  
 a plurality of input/output disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers; and  
 at least one column select line disposed in a portion of the third conductive layer formed above the sense amplifier region, each column select line coupled to at least some of the sense amplifiers.  
 
     
     
       7. The memory-cell array of  claim 6  wherein the first, second, and third conductive layers include polysilicon, first metal, and second metal layers, respectively. 
     
     
       8. The memory-cell array of  claim 6  wherein the input/output lines are substantially parallel to the digit lines and the column select lines are substantially perpendicular to the digit lines. 
     
     
       9. A memory device formed in a semiconductor substrate and including address, data, and control buses, comprising:
 an array of memory cells formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns;  
 a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row;  
 a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column;  
 a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines;  
 a plurality of input/output disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers;  
 at least one column select line disposed in a portion of the third conductive layer formed above the sense amplifier region, each column select line coupled to at least some of the sense amplifiers;  
 a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;  
 a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and activating a column select line corresponding to the decoded column address;  
 a data path circuit coupled to the data bus and operable to transfer data placed on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and  
 a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received on the control bus.  
 
     
     
       10. The memory device of  claim 9 , further including several banks of arrays, each bank including input/output lines transferring data to and from the data path circuit. 
     
     
       11. The memory device of  claim 9  wherein the memory device comprises an SLDRAM. 
     
     
       12. The memory device of  claim 9  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       13. The memory device of  claim 9  wherein the first conductive layer includes a polysilicon layer, the second conductive layer includes a first metal layer, and the third conductive layer includes a second metal layer. 
     
     
       14. The memory device of  claim 9  wherein the memory-cell array includes 512 input/output lines and two column select lines. 
     
     
       15. An Embedded DRAM, comprising:
 logic circuitry formed in a semiconductor substrate having address, data and control busses;  
 an array of memory cells formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns;  
 a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row;  
 a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column;  
 a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines;  
 a plurality of input/output lines disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers;  
 at least one column select line disposed in a portion of the third conductive layer formed above the sense amplifier region, each column select line coupled to at least some of the sense amplifiers;  
 a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;  
 a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and activating a column select line corresponding to the decoded column address;  
 a data path circuit coupled to the data bus and to the input/output lines of the array, the data path circuit operable to transfer data received on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and  
 a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received from the logic circuitry on the control bus.  
 
     
     
       16. The Embedded DRAM of  claim 15  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       17. The Embedded DRAM of  claim 15  wherein the first conductive layer includes a polysilicon layer, the second conductive layer includes a first metal layer, and the third conductive layer includes a second metal layer. 
     
     
       18. A packetized dynamic random access memory formed in a semiconductor substrate, comprising:
 a clock generator circuit generating an internal clock signal having a phase relative to an external clock signal determined by a phase command signal;  
 at least one array of memory cells adapted to store data at a location determined by a row address and a column address, the array formed in the semiconductor substrate and including, 
 a plurality of memory cells arranged in rows and columns, the memory cells formed in an array region of the substrate,  
 a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row,  
 a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column,  
 a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines,  
 a plurality of input/output disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers, and  
 at least one column select line disposed in a portion of the third conductive layer formed above the sense amplifier region, each column select line coupled to at least some of the sense amplifiers;  
 
 a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;  
 a column address circuit adapted to receive or apply data over the plurality of input/output lines to memory cells in the selected row corresponding to the column address responsive to a second set of command signals;  
 a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to a third set of command signals; and  
 a command generator receiving command packets indicative of a command, a row address and a command address, the command generator applying the first, second, and third sets of command signals to the row address circuit, column address circuit, and data path circuit, respectively, to transfer data to and from the packetized dynamic random access memory.  
 
     
     
       19. The packetized dynamic random access memory of  claim 18  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       20. The packetized dynamic random access memory of  claim 18  wherein the first conductive layer includes a polysilicon layer, the second conductive layer includes a first metal layer, and the third conductive layer includes a second metal layer. 
     
     
       21. The packetized dynamic random access memory of  claim 18  wherein the memory-cell array includes 512 input/output lines and two column select lines. 
     
     
       22. A computer system, comprising:
 a processor having a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;  
 an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and  
 a packetized dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the packetized dynamic random access memory including. ,  
 a clock generator circuit generating an internal clock signal having a phase relative to an external clock signal determined by a phase command signal;  
 at least one array of memory cells adapted to store data at a location determined by a row address and a column address, the array formed formed in the semiconductor substrate and including, 
 a plurality of memory cells arranged in rows and columns, the memory cells formed in an array region of the substrate,  
 a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row. ,  
 a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column. ,  
 a plurality of sense amplifiers farmed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines,  
 a plurality of input/output disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers, and  
 at least one column select line disposed in a portion of the third conductive layer formed above the sense amplifier region, each column select line coupled to at least some of the sense amplifiers;  
 
 a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;  
 a column address circuit adapted to receive or apply data over the plurality of input/output lines to memory cells in the selected row corresponding to the column address responsive to a second set of command signals;  
 a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to a third set of command signals; and  
 a command generator receiving command packets indicative of a command, a row address and a command address, the command generator applying the first, second, and third sets of command signals to the row address circuit, column address circuit, and data path circuit, respectively, to transfer data to and from the packetized dynamic random access memory.  
 
     
     
       23. The computer system of  claim 22  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       24. The computer system of  claim 22  wherein the first conductive layer includes a polysilicon layer, the second conductive layer includes a first metal layer, and the third conductive layer includes a second metal layer. 
     
     
       25. The computer system of  claim 22  wherein the memory-cell array includes 512 input/output lines and two column select lines. 
     
     
       26. A memory- cell array formed in a semiconductor substrate, comprising:      a plurality of memory cells arranged in rows and columns, the memory cells formed in an array region of the substrate;        a plurality of complementary pairs of digit lines formed in the array region, each complementary pair coupled to a plurality of memory cells in an associated column;        a plurality of word lines formed in the array region, each word line coupled to each memory cell in an associated row;        a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines;        a plurality of input/output lines formed adjacent the array region, each input/output line coupled to at least a pair of the sense amplifiers through a respective switch; and        at least one column select line formed adjacent the sense amplifier region, each column select line coupled to a control input of a plurality of the switches of respective sense amplifiers.     
     
     
       27. A memory- cell array formed in a semiconductor substrate, comprising:      an array of memory cells formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns;        a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row;        a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column;        a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines;        a plurality of input/output lines disposed in a third conductive layer formed adjacent the array region, each input/output line coupled to at least one of the sense amplifiers;        at least one column select line disposed in a portion of the third conductive layer formed adjacent the sense amplifier region, each column select line coupled to at least some of the sense amplifiers.     
     
     
       28. A memory device formed in a semiconductor substrate and including address, data, and control buses, comprising:
   an array of memory cells formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns;        a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row;        a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column;        a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines;        a plurality of input/output lines disposed in a third conductive layer formed adjacent the array region, each input/output line coupled to at least one of the sense amplifiers;        at least one column select line disposed in a portion of the third conductive layer formed adjacent the sense amplifier region, each column select line coupled to at least some of the sense amplifiers;        a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;        a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and activating a column select line corresponding to the decoded column address;        a data path circuit coupled to the data bus and operable to transfer data placed on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and        a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received on the control bus.     
     
     
       29. An Embedded DRAM, comprising:
   logic circuitry formed in a semiconductor substrate, and including address, data, and control busses;        an array of memory cells formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns;        a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row;        a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column;        a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines;        a plurality of input/output lines disposed in a third conductive layer formed adjacent the array region, each input/output line coupled to at least one of the sense amplifiers;        at least one column select line disposed in a portion of the third conductive layer formed adjacent the sense amplifier region, each column select line coupled to at least some of the sense amplifiers;        a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;        a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and activating a column select line corresponding to the decoded column address;        a data path circuit coupled to the data bus and operable to transfer data placed on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and        a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received from the logic circuitry on the control bus.     
     
     
       30. A packetized dynamic random access memory formed in a semiconductor substrate, comprising:
   a clock generator circuit generating an internal clock signal having a phase relative to an external clock signal determined by a phase command signal;        at least one array of memory cells adapted to store data at a location determined by a row address and a column address, the array formed in the semiconductor substrate and including,      a plurality of memory cells arranged in rows and columns, the memory cells formed in an array region of the substrate,        a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row,        a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column,        a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines,        a plurality of input/output lines disposed in a third conductive layer formed adjacent the array region, each input/output line coupled to at least one of the sense amplifiers, and        at least one column select line disposed in a portion of the third conductive layer formed adjacent the sense amplifier region, each column select line coupled to at least some of the sense amplifiers;          a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;        a column address circuit adapted to receive or apply data over the plurality of input/output lines to memory cells in the selected row corresponding to the column address responsive to a second set of command signals;        a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to a third set of command signals; and        a command generator receiving command packets indicative of a command, a row address and a command address, the command generator applying the first, second, and third sets of command signals to the row address circuit, column address circuit, and data path circuit, respectively, to transfer data to and from the packetized dynamic random access memory.     
     
     
       31. A computer system, comprising:
   a processor having a processor bus;        an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;        an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and        a packetized dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the packetized dynamic random access memory including,        a clock generator circuit generating an internal clock signal having a phase relative to an external clock signal determined by a phase command signal;        at least one array of memory cells adapted to store data at a location determined by a row address and a column address, the array formed in the semiconductor substrate and including,      a plurality of memory cells arranged in rows and columns, the memory cells formed in an array region of the substrate,        a plurality of word lines formed in the array region from a first conductive layer, each word line coupled to each memory cell in an associated row,        a plurality of complementary pairs of digit lines formed in the array region from a second conductive layer, each complementary pair coupled to a plurality of memory cells in an associated column,        a plurality of sense amplifiers formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier coupled to an associated pair of complementary digit lines,        a plurality of input/output lines disposed in a third conductive layer formed adjacent the array region, each input/output line coupled to at least one of the sense amplifiers, and        at least one column select line disposed in a portion of the third conductive layer formed adjacent the sense amplifier region, each column select line coupled to at least some of the sense amplifiers;          a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;        a column address circuit adapted to receive or apply data over the plurality of input/output lines to memory cells in the selected row corresponding to the column address responsive to a second set of command signals;        a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to a third set of command signals; and        a command generator receiving command packets indicative of a command, a row address and a command address, the command generator applying the first, second, and third sets of command signals to the row address circuit, column address circuit, and data path circuit, respectively, to transfer data to and from the packetized dynamic random access memory.     
     
     
       32. A memory- cell array formed in a semiconductor substrate, comprising:      a plurality of memory cells arranged in rows and columns;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of word lines each coupled to the memory cells in an associated row;        a plurality of sense amplifiers each coupled to a respective digit line;        a plurality of input/output lines each coupled to at least a pair of the sense amplifiers through a respective switch; and        at least two column select lines each coupled to a control input of a plurality of the switches, each switch being coupled to first and second column select lines, and being operable to couple an associated data line to one of two associated sense amplifiers responsive to respective column select signals received on the first and second column lines.     
     
     
       33. The memory- cell array of    claim 32    wherein each switch includes an NMOS transistor.   
     
     
       34. The memory- cell array of    claim 32    wherein the memory - cell array includes  512  input/output lines and two column select lines.   
     
     
       35. The memory- cell array of    claim 32    wherein the input/output lines are formed substantially parallel to the digit lines and the column select lines are substantially perpendicular to the digit lines.   
     
     
       36. The memory- cell array of    claim 32    wherein a pair of complimentary digit lines are coupled to each of the sense amplifiers.   
     
     
       37. The memory- cell array of    claim 36    wherein each pair of complimentary digit lines extend through the same array of memory cells in a folded digit line architecture.   
     
     
       38. A memory device formed in a semiconductor substrate and including address, data, and control buses, comprising:
   an array of memory cells arranged in rows and columns;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of word lines each coupled to each memory cell in an associated row;        a plurality of sense amplifiers each coupled to a respective digit line;        a plurality of input/output lines disposed substantially parallel to the digit lines;        a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;        a plurality of switches each coupled between a respective sense amplifier and one of the input/output lines;        at least two column select lines each coupled to a respective control input of a plurality of the switches, the column select lines being disposed substantially perpendicular to the digit lines;        a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and activating a column select line corresponding to the decoded column address;        a data path circuit coupled to the data bus and operable to transfer data placed on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and        a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received on the control bus.     
     
     
       39. The memory device of  claim 38 , further including several banks of arrays, each bank including input/output lines transferring data to and from the data path circuit. 
     
     
       40. The memory device of  claim 38  wherein the memory device comprises an SLDRAM. 
     
     
       41. The memory device of  claim 38  wherein the array of memory cells includes  512  input/output lines and two column select lines. 
     
     
       42. The memory device of  claim 38  wherein a pair of complimentary digit lines are coupled to each of the sense amplifiers. 
     
     
       43. The memory device of  claim 42  wherein each pair of complimentary digit lines extend through the same array of memory cells in a folded digit line architecture. 
     
     
       44. A memory device formed in a semiconductor substrate and including address, data, and control buses, comprising:
   an array of memory cells arranged in rows and columns, the array of memory cells comprising  512  input/output lines and  2  column select lines;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of word lines each coupled to each memory cell in an associated row;        a plurality of sense amplifiers each coupled to a respective digit line;        a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;        a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and causing a plurality of the sense amplifiers corresponding to the decoded column address to be coupled to respective ones of the input/output lines;        a data path circuit coupled to the data bus and operable to transfer data placed on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and        a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received on the control bus.     
     
     
       45. The memory device of  claim 44 , further including several banks of arrays, each bank including input/output lines transferring data to and from the data path circuit. 
     
     
       46. The memory device of  claim 44  wherein the memory device comprises an SLDRAM. 
     
     
       47. The memory device of  claim 44  wherein the input/output lines are disposed substantially parallel to the digit lines. 
     
     
       48. The memory device of  claim 44  wherein a pair of complimentary digit lines are coupled to each of the sense amplifiers. 
     
     
       49. The memory device of  claim 48  wherein each pair of complimentary digit lines extend through the same array of memory cells in a folded digit line architecture. 
     
     
       50. An Embedded DRAM, comprising:
   logic circuitry formed in a semiconductor substrate having address, data, and control busses;        an array of memory cells arranged in rows and columns;        a plurality of word lines each coupled to each memory cell in an associated row;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of sense amplifiers each coupled to an associated one of the digit lines;        a plurality of input/output lines;        a plurality of switches each coupled between a respective one of the sense amplifiers and one of the input/output lines;        a pair of column select lines each coupled to a respective control terminal of a plurality of the switches;        a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;        a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and activating a column select line corresponding to the decoded column address;        a data path circuit coupled to the data bus and to the input/output lines of the array, the data path circuit operable to transfer data received on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and        a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received from the logic circuitry on the control bus.     
     
     
       51. The Embedded DRAM of  claim 50  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       52. The Embedded DRAM of  claim 50  wherein each of the sense amplifiers is coupled to a pair of complimentary digit lines that extend through the same array of memory cells in a folded digit line architecture. 
     
     
       53. An Embedded DRAM, comprising:
   logic circuitry formed in a semiconductor substrate having address, data and control busses;        an array of memory cells arranged in rows and columns;        a plurality of word lines each coupled to each memory cell in an associated row;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of sense amplifiers each coupled to an associated one of the digit lines;        a plurality of input/output lines;        a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;        a column address decoder coupled to the address bus and to column select lines, the column address decoder decoding a column address applied on the address bus and causing a plurality of the sense amplifiers corresponding to the decoded column address to be coupled to respective ones of the input/output lines;        a data path circuit coupled to the data bus and to the input/output lines of the array, the data path circuit operable to transfer data received on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and        a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received from the logic circuitry on the control bus.     
     
     
       54. The Embedded DRAM of  claim 53  wherein the input/output lines are disposed substantially parallel to the digit lines. 
     
     
       55. The Embedded DRAM of  claim 53  wherein each of the sense amplifiers is coupled to a pair of complimentary digit lines that extend through the same array of memory cells in a folded digit line architecture. 
     
     
       56. A packetized dynamic random access memory formed in a semiconductor substrate, comprising:
   a clock generator circuit generating an internal clock signal having a phase relative to an external clock signal determined by a phase command signal;        at least one memory array comprising:      a plurality of memory cells arranged in rows and columns, the memory cells adapted to store data at a location determined by a row address and a column address in a packet;        a plurality of word lines each coupled to each memory cell in an associated row;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of sense amplifiers each coupled to an associated digit line;        a plurality of input/output lines;        a plurality of switches each coupled to between a respective one of the sense amplifiers and one of the input/output lines, and        a pair of column select lines each coupled to a respective control input of a plurality of the switches;          a row address circuit adapted to receive and decode the row address, and activate a word line corresponding to the row address responsive to a first set of command signals;        a column address circuit adapted to receive and decode the column address, the column address circuit activating a column select line corresponding to the decoded column address responsive to a second set of command signals;        a data path circuit adapted to couple data between an external terminal and the input/output lines responsive to a third set of command signals; and        a command generator receiving command packets indicative of a command, a row address and a command address, the command generator applying the first, second, and third sets of command signals to the row address circuit, column address circuit, and data path circuit, respectively, to transfer data to and from the packetized dynamic random access memory.     
     
     
       57. The packetized dynamic random access memory of  claim 56  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       58. The packetized dynamic random access memory of  claim 56  wherein the memory- cell array includes  512  input/output lines and two column select lines.   
     
     
       59. The packetized dynamic random access memory of  claim 56  wherein each of the sense amplifiers is coupled to a pair of complimentary digit lines that extend through the same array of memory cells in a folded digit line architecture. 
     
     
       60. A computer system, comprising:
   a processor having a processor bus;        an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;        an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and        a memory device coupled to the processor through the processor bus, the memory device including address, data, and control buses, the memory device comprising:      an array of memory cells arranged in rows and columns;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of word lines each coupled to each memory cell in an associated row;        a plurality of sense amplifiers each coupled to a respective digit line;        a plurality of input/output lines;        a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;        a plurality of switches each coupled between a respective sense amplifier and one of the input/output lines;        at least two column select lines each coupled to a respective control input of a plurality of the switches;        a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and activating a column select line corresponding to the decoded column address;          a data path circuit coupled to the data bus and operable to transfer data placed on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and        a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received on the control bus.     
     
     
       61. The computer system of  claim 60 , further including several banks of arrays, each bank including input/output lines transferring data to and from the data path circuit. 
     
     
       62. The computer system of  claim 60  wherein the memory device comprises an SLDRAM. 
     
     
       63. The computer system of  claim 60  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       64. The computer system of  claim 60  wherein the array of memory cells includes  512  input/output lines and two column select lines. 
     
     
       65. The computer system of  claim 60  wherein a pair of complimentary digit lines are coupled to each of the sense amplifiers. 
     
     
       66. The computer system of  claim 60  wherein each pair of complimentary digit lines extend through the same array of memory cells in a folded digit line architecture. 
     
     
       67. A computer system, comprising:
   a processor having a processor bus;        an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;        an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and        an embedded DRAM coupled to the processor through the processor bus, the embedded DRAM comprising:      logic circuitry formed in a semiconductor substrate having address, data, and control busses;        an array of memory cells arranged in rows and columns;        a plurality of word lines each coupled to each memory cell in an associated row;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of sense amplifiers each coupled to an associated one of the digit lines;        a plurality of input/output lines;        a plurality of switches each coupled between a respective one of the sense amplifiers and one of the input/output lines;        a pair of column select lines each coupled to a respective control terminal of a plurality of the switches;        a row address decoder coupled to the address bus and to the word lines, the row address decoder decoding a row address applied on the address bus and activating a word line corresponding to the decoded row address;        a column address decoder coupled to the address bus and to the column select lines, the column address decoder decoding a column address applied on the address bus and activating a column select line corresponding to the decoded column address;        a data path circuit coupled to the data bus and to the input/output lines of the array, the data path circuit operable to transfer data received on the input/output lines to the data bus during read operations and to transfer data applied on the data bus to the input/output lines during write operations; and        a control circuit coupled to the control bus, row and column address decoders, and data path circuit, operable to control such decoders and data path circuit responsive to control signals received from the logic circuitry on the control bus.       
     
     
       68. The computer system of  claim 67  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       69. The computer system of  claim 67  wherein each of the sense amplifiers is coupled to a pair of complimentary digit lines that extend through the same array of memory cells in a folded digit line architecture. 
     
     
       70. A computer system, comprising:
   a processor having a processor bus;        an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;        an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and        a packetized dynamic random access memory coupled to the processor bus to receive a packet from the processor, the packetized dynamic random access memory comprising:      a clock generator circuit generating an internal clock signal having a phase relative to an external clock signal determined by a phase command signal;        at least one memory array comprising:      a plurality of memory cells arranged in rows and columns, the memory cells adapted to store data at a location determined by a row address and a column address in a packet;        a plurality of word lines each coupled to each memory cell in an associated row;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of sense amplifiers each coupled to an associated digit line;        a plurality of input/output lines;        a plurality of switches each coupled to between a respective one of the sense amplifiers and one of the input/output lines, and        a pair of column select lines each coupled to a respective control input of a plurality of the switches;            a row address circuit adapted to receive and decode the row address, and activate a word line corresponding to the row address responsive to a first set of command signals;        a column address circuit adapted to receive and decode the column address, the column address circuit activating a column select line corresponding to the decoded column address responsive to a second set of command signals;        a data path circuit adapted to couple data between an external terminal and the input/output lines responsive to a third set of command signals; and        a command generator receiving command packets indicative of a command, a row address and a command address, the command generator applying the first, second, and third sets of command signals to the row address circuit, column address circuit, and data path circuit, respectively, to transfer data to and from the packetized dynamic random access memory.     
     
     
       71. The computer system of  claim 70  wherein the input/output lines are disposed substantially parallel to the digit lines and the column select lines are disposed substantially perpendicular to the digit lines. 
     
     
       72. The computer system of  claim 70  wherein the memory- cell array includes  512  input/output lines and two column select lines.   
     
     
       73. A memory- cell array formed in a semiconductor substrate, comprising:      a plurality of memory cells arranged in rows and columns;        a plurality of digit lines each coupled to a plurality of memory cells in an associated column;        a plurality of word lines each coupled to the memory cells in an associated row;        a plurality of sense amplifiers each coupled to a respective digit line;        a plurality of input/output lines each coupled to at least a pair of the sense amplifiers through a respective switch, the input/output lines being formed substantially parallel to the digit lines; and        at least two column select lines each coupled to a control input of a plurality of the switches, the column select lines being substantially perpendicular to the digit lines.     
     
     
       74. The memory- cell array of    claim 73    wherein each switch includes an NMOS transistor.   
     
     
       75. The memory- cell array of    claim 73    wherein the memory - cell array includes  512  input/output lines and two column select lines.   
     
     
       76. The memory- cell array of    claim 73    wherein each switch is coupled to first and second column select lines, and couples an associated data line to one of two associated sense amplifiers responsive to respective column select signals received on the first and second column lines.   
     
     
       77. The memory- cell array of    claim 76    wherein each pair of complimentary digit lines extend through the same array of memory cells in a folded digit line architecture.