Memory module assembly using partially defective chips

Abstract

Methods and devices for using less-than-perfect memory chips and packages in the manufacture of memory modules. In the preferred method the failed I/O lines in primary memory packages are disconnected and replaced by selected I/O lines from flawless or partially defective backup parts all mounted on the same module. The various processes comprise sorting of partially defective parts according to the results of wafer or packages test, judicious distribution of backup parts on a PC board module and routing of their I/O lines, optimized patching techniques and multi-level tests and repatching routines. The methods and processes are equally applicable to Chip On Board assemblies as well as package assemblies.

1. A method for developing a fully functional transparent memory module comprising an assembly of selected independent primary and backup memory parts,
 the method comprising the steps of: 
 testing a plurality of independent memory parts for failed I/O data line segments;  
 sorting the parts according to the results of the testing;  
 identifying failed and working I/O data line segments in the sorted parts;  
 selecting at least one primary part having at least one I/O data line failure, and at least one different partially defective backup memory part from said sorted parts; and  
 combining working I/O data line segments of different selected memory parts, including at least one working I/O data line segment of at least one partially defective backup memory part and working I/O data line segments of a primary part to form a fully functional transparent memory module.  
 
 
     
     
       2. A memory module made by the method of  claim 1 . 
     
     
       3. The method of  claim 1 , where at least one of the memory parts is a package. 
     
     
       4. The method of  claim 1 , further comprising:
 testing the completed memory module as to its operational status to approve the module for use or to identify any operating problems; and, as required, changing the combination of working segments of memory parts to overcome any such identified problem.  
 
     
     
       5. A memory module formed by the method of  claim 4 . 
     
     
       6. The method of  claim 1 , wherein the combination of working segments is done by patching using solder-dot connections on a printed circuit board. 
     
     
       7. The method of  claim 1 , wherein the combination of working segments is done by patching using jumper installations on a printed circuit board. 
     
     
       8. A method for developing effective chip-on-board memory modules comprising an assembly of a selected combination of independent partially defective memory chips,
 comprising the steps of: 
 assembling the selected chips as primary chips and backup chips onto a chip-on-board memory module assembly;  
 testing the assembled module for failed I/O data lines in the chips;  
 identifying operating I/O data line segments in the chips; and  
 combining identified working I/O data line segments of a partially defective primary chip with a required number of working I/O data line segments of backup memory chips.  
 
 
     
     
       9. A chip-on-board memory module made by the method of  claim 8 . 
     
     
       10. The method of  claim 8  further comprising the steps of:
 pretesting the parts while in die form; and  
 sorting the parts according to the results of the pretesting.  
 
     
     
       11. A chip-on-board memory module made by the method in  claim 10 . 
     
     
       12. A method for patching selected partially defective independent primary memory parts with selected different partially defective independent backup memory parts to form a memory module functionally transparent to the user, comprising the steps of:
 testing the primary memory parts and the backup memory parts before mounting the parts on a board to;  
 identify operating and failed I/O data line segments of the primary parts and of the backup memory parts;  
 determining which operating I/O data lines from the backup memory parts to use for selectively patching failed I/O data lines segments of the primary memory parts; and  
 substituting said determined operating I/O data lines from the backup parts for failed I/O data lines in one or more primary parts to form a completed memory module.  
 
     
     
       13. A memory module made by the method of  claim 12 . 
     
     
       14. The method of  claim 12  wherein the resultant memory module comprises all good and partially defective memory parts. 
     
     
       15. The method of  claim 12 , further comprising;
 testing the completed memory module as to its operational status to approve the module for use or to identify any operating problems; and, as required,  
 the step of replacing at least one of the parts with a replacement part to overcome any such identified operating problem.  
 
     
     
       16. A memory module made by the method of  claim 15 , wherein the memory module comprises all good, partially defective, and replacement parts. 
     
     
       17. The method of  claim 12 , wherein the patching is done by using solder-dot connections on a printed circuit board. 
     
     
       18. The method of  claim 12 , wherein the patching is done using jumper installations on a printed circuit board. 
     
     
       19. A method for patching primary parts with partially defective parts, comprising the steps of:
 perform a wafer test on memory die;  
 identify the working and nonworking segments in the parts;  
 package the primary and partially defective parts according to working segments;  
 test the parts;  
 give each part an identification code, the identification code containing a quadrant test pattern of the part;  
 select parts for assembly on a module board;  
 assemble the parts on the module board according to the nature and location of the parts' working segments;  
 fill in the solder-dot locations of the primary parts, wherein the solder-dot locations of the back-up parts are left open;  
 test the module on a full function circuit tester, wherein failed bits are noted, and the module is assigned a new identification code designating the failed bits;  
 generate patching instruction charts for the module, wherein the development of the patching instruction charts includes an optimization pass designed to maximize use of smaller patch parts, leaving the larger parts available for patching later-discovered failures;  
 disconnect solder-dot connections on the primary parts to isolate the failed line;  
 fill the solder-dot connections to patch in the substitute lines, the solder-dot connections selected as identified in the patching instruction charts; and  
 re-test the module, including high temperature stress testing of the module.  
 
     
     
       20. The method of  claim 19  wherein the disconnecting and filling steps are automated. 
     
     
       21. A memory module made by the method of  claim 19 . 
     
     
       22. The method of  claim 19  wherein the resultant memory module comprises all good and partially defective memory parts. 
     
     
       23. The method of  claim 19 , further comprising the step of replacing at least one of the parts with a replacement part. 
     
     
       24. A memory module made by the method of  claim 19 , wherein the memory module comprises all good, partially defective and replacement parts. 
     
     
       25. A method for generating patching instruction traveler charts using optimization, comprising the following steps:
 scanning bits of wider parts;  
 identifying unused bits in the smaller parts, wherein the unused bits will be used for substitution;  
 optimizing the selection of the parts to use in patching;  
 generating patching instructions; and  
 implementing the generated patching instructions into a traveler chart.  
 
     
     
       26. The method of  claim 25 , wherein at least one computer is used to automate all of the steps. 
     
     
       27. A module made up of primary parts and partially defective backup parts, comprising:
 at least one primary part, the primary part having at least one line failure;  
 a plurality of partially defective parts;  
 a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts.  
 
     
     
       28. The module of  claim 27 , wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the substitute line having the equivalent function as the failing line so that the module is transparent to the user. 
     
     
       29. The module of  claim 27  wherein the module comprises all good and partially defective memory parts. 
     
     
       30. The module of  claim 27 , wherein the module contains at least one replacement part. 
     
     
       31. The module of  claim 27 , wherein the module comprises all good, partially defective and replacement parts. 
     
     
       32. The module of  claim 27  wherein the selection of substitute lines are identified in patching instruction charts developed for the module, wherein the development of the patching instruction charts includes part optimization. 
     
     
       33. A SIMM module made up of primary parts and partially defective parts, comprising:
 at least two primary parts, at least one of the primary parts having at least one line failure;  
 a plurality of partially defective parts;  
 a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing the failing primary part lines to be replaced by I/O substitute lines from the partially defective parts;  
 wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the substitute line having the equivalent function as the failing line so that the module is transparent to the user.  
 
     
     
       34. The module of  claim 33  wherein the selection of substitute lines are identified in patching instruction charts developed for the module, wherein the development of the patching instruction charts includes part optimization. 
     
     
       35. The module of  claim 33  wherein the module comprises all good and partially defective memory parts. 
     
     
       36. The module of  claim 33 , wherein the module contains at least one replacement part. 
     
     
       37. A module of  claim 33 , wherein the memory module comprises all good, partially defective and the replacement parts. 
     
     
       38. The module of  claim 33 , wherein the primary parts are 1MX16 parts. 
     
     
       39. The module of  claim 38 , wherein the partially defective parts are 1MX4 parts. 
     
     
       40. A memory module made up of primary parts and partially defective backup parts, comprising:
 four primary parts, each of the primary parts having at least one line failure;  
 eight partially defective backup parts;  
 a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing the failing primary part lines to be replaced by I/O substitute lines from the backup parts;  
 wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the module is transparent to the user.  
 
     
     
       41. The memory module of  claim 40 , wherein the memory module is a 2MX32 memory module, the four primary parts consist of 1MX16 packages, and the backup parts consist of eight 1MX4 packages. 
     
     
       42. The memory module of  claim 40 , wherein each line in a primary part can be patched by a line from either one of the eight partially defective backup parts. 
     
     
       43. The module of  claim 40 , wherein the selection of substitute lines are identified in patching instruction charts developed for the memory module, wherein the development of the patching instruction charts includes part optimization. 
     
     
       44. The module of  claim 40  wherein the memory module comprises all good and partially defective memory parts. 
     
     
       45. The module of  claim 40 , wherein the memory module contains at least one replacement part. 
     
     
       46. A module of  claim 40 , wherein the memory module comprises all good, partially defective and the replacement parts. 
     
     
       47. A chip-on-board module made up of primary parts and partially defective backup parts, comprising:
 at least one primary part, the primary part having at least one line failure;  
 a plurality of partially defective parts;  
 a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts;  
 wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the chip-on-board module is transparent to the user.  
 
     
     
       48. The memory module of  claim 47 , wherein the four primary parts consist of 1MX16 parts, and the backup parts consist of eight 1MX4 parts. 
     
     
       49. The module of  claim 47 , wherein the selection of substitute lines are identified in patching instruction charts developed for the module, wherein the development of the patching instruction charts includes part optimization. 
     
     
       50. A method for selecting and assembling primary parts and backup parts on a chip-on-board module assembly comprising patterns of solder dot locations for the primary and backup parts, the process comprising the steps of:
 performing a wafer test on a memory die;  
 selecting, as primary parts, partially defective dies that have a reasonable probability of being patched successfully;  
 selecting, as backup parts, other partially defective dies that test to be suitable for patching;  
 assembling the selected primary and backup parts on the PC module;  
 applying a plastic over coating to the assembled parts; and  
 testing the module using a chip test applied at the module pins; and  
 patching failed segments of the primary parts with working segments of the backup parts.  
 
     
     
       51. A method for selecting and assembling primary parts and backup parts on a chip-on-board module assembly comprising patterns of solder dot locations for the primary and backup parts,
 the process comprising the steps of: 
 performing a wafer test on a memory die;  
 selecting, as primary parts, dies that have a reasonable probability of being patched successfully;  
 selecting, as backup parts, other dies for assembly on a PC module;  
 assembling the selected primary and backup parts on the PC module;  
 applying a plastic over coating to the assembled parts; and  
 test the module using a chip test applied at the module pins;  
 assigning a bar code to the module to identify failed bits;  
 fill in the solder-dot locations of the primary parts, the solder-dot locations of the back-up parts are left open;  
 test the module on a full function circuit tester, wherein failed bits are noted, and the module is assigned a bar-code identifying the failed bits;  
 generate patching instruction charts for the module, wherein the development of the patching instruction charts includes an optimization pass designed to maximize use of smaller patch parts, leaving the larger parts available for patching later-discovered failures;  
 disconnect solder-dot connections on the primary parts to isolate any failed line;  
 fill the solder-dot connections to patch in substitute lines, the solder-dot connections selected as identified in the patching instruction charts;  
 re-test the module, including high temperature stress testing of the module.  
 
 
     
     
       52. The method of  claim 51  wherein the disconnecting and filling steps are automated. 
     
     
       53. A memory module made up of primary parts and partially defective backup parts, comprising:
 at least four primary parts, the primary parts having at least one line failure, and the primary parts are laid out horizontally with a card edge;  
 at least four partially defective parts;  
 a module PC board containing a pattern of solder-dot connections, the solder-dot connections allowing any failing primary part I/O lines to be replaced by I/O substitute lines from the backup parts;  
 wherein the failing line is disconnected from the primary part by removing the solder of its solder dot connection and the substitute line is connected by filling the applicable solder-dot, the replacement line having the equivalent function as the failing line so that the module is transparent to the user.  
 
     
     
       54. The memory module of  claim 53 , wherein the four primary parts consist of 1MX16 parts, and the backup parts consists of 1MX4 memory parts. 
     
     
       55. The memory module of  claim 53 , wherein two primary parts and two back-up parts are located on the front side of the board and the other two primary parts and the other two back-up parts are located on the back side of the board. 
     
     
       56. The memory module of  claim 53 , wherein at least one of the primary parts is an extended data out part that runs at about 60 nsec. 
     
     
       57. The memory module of  claim 53 , wherein at least one of the primary parts is a extended data out part that runs at about 70 nsec. 
     
     
       58. The memory module of  claim 53 , wherein at least one of the primary parts is a Fast Page part. 
     
     
       59. The memory module of  claim 53 , further comprising a variable voltage regulator, the variable voltage regulator connected to the module PC board. 
     
     
       60. The memory module of  claim 53 , further comprising a variable voltage regulator, the variable voltage regulator connected to the module PC board, wherein the variable voltage regulator works with the extended data out primary part by tying output enable to ground. 
     
     
       61. The memory module of  claim 53 , further comprising a variable voltage regulator, the variable voltage regulator connected to the module PC board, wherein the variable voltage regulator works with the Fast Page primary part by tying output enable to ground. 
     
     
       62. The module of  claim 53  wherein the resultant memory module comprises all good and partially defective memory parts. 
     
     
       63. The module of  claim 53 , wherein the resultant memory module contains at least one replacement part. 
     
     
       64. A module of  claim 53 , wherein the memory module comprises all good, partially defective and the replacement parts. 
     
     
       65. A memory module comprising:
 primary part memory means for storing data;  
 independent backup part memory means for storing data;  
 connection means for selectively substituting an operational I/O data line of said backup memory means for a failed I/O data line of said primary memory means;  
 said memory module has a target memory capability X,  
 said primary part memory means has a memory capacity X minus the capacity of any defective I/O data lines therein; and  
 said independent backup part memory means has available memory capacity at least equal to the capacity of said defective I/O data lines.  
 
     
     
       66. A memory module in accordance with  claim 65  wherein:
 said connection means comprises a pattern of solder dot connections.  
 
     
     
       67. A memory module in accordance with  claim 65  wherein:
 said connection means comprises a pattern of jumper wire connections.  
 
     
     
       68. A memory module in accordance with  claim 65  wherein:
 said primary part memory means comprise 1MX16 parts; and  
 said backup part memory means comprise 1MX4 parts.  
 
     
     
       69. A method for constructing a fully functional memory module which utilizes partially defective independent memory circuit parts comprising:
 (a) testing and classifying memory parts in a set of defined classifications;  
 (b) selecting a primary memory part having a selected classification;  
 (c) selecting a backup memory part having a selected different classification;  
 (d) constructing a memory module wherein any defective data lines of the selected primary memory part are replaced by operational data lines of the backup circuit structure; and  
 (e) testing constructing step (d) comprises: providing a selected pattern of solder dot connections.  
 
     
     
       70. A memory module constructed in accordance with any of  the claims  method of claim  69 . 
     
     
       71. A method for constructing a fully functional memory module which utilizes partially defective independent memory circuit parts comprising:
 (a) testing and classifying memory parts in a set of defined classifications  
 (b) selecting a primary memory part having a selected classification;  
 (c) selecting a backup memory part having a selected different classification;  
 (d) constructing a memory module wherein:  any defective data lines of the selected primary memory part are replaced by operational data lines of the backup circuit structure;  
 (e) testing said so constructed module as to its operational status to approve use of said module or to identify any operating problem in said module;  
 (f) reconstructing said module to remove any identified operating problem;  
 (g) testing said module as to its operational status to approve use as reconstructed or to identify any operating problems; and  
 (j)( h ) repeating steps (h) and (i)( f )  and  ( g ) as required until the module is approved for service.  
 
     
     
       72. A method of manufacturing a fully functional transparent memory module including an assembly of selected independent primary and independent backup memory parts, the method comprising the steps of:
   testing a plurality of independent memory parts to identify failed I/O data line segments and working I/O data line segments,        sorting said tested memory parts into a plurality of categories by patterns of failed and working I/O data line segments,        selecting at least one primary part having at least one failed I/O segment, and at least one partially defective backup part from said sorted parts, and        combining working I/O data line segments of different selected primary parts and of partially defective backup parts to form a fully functional transparent memory module.     
     
     
       73. The method of manufacturing a fully functional memory module of  claim 72  wherein said step of selecting includes utilizing primary parts and backup memory parts from different categories of tested parts and additionally includes the step of optimizing use of a smaller working segment of said backup memory part to leave larger working segments of said backup parts available for subsequent I/O segment failure repair. 
     
     
       74. The method of manufacturing a fully functional transparent memory module of  claim 72  additionally including the step of mounting said selected primary parts and said selected backup memory parts on a printed circuit type board having a plurality of conductive strips connectable to respective I/O data line segments of said primary parts and the additional step of positioning said selected primary parts and said selected backup memory parts on said printed circuit board in accordance with the location of each part's working segments relative to said primary parts. 
     
     
       75. The method of manufacturing a fully functional memory module of  claim 74  wherein the step of combining working I/O data segments includes selectively interrupting at least one of said conductive strips of said printed circuit board and connecting the interrupted line segment to replace it with a selected working line segment of a backup memory part. 
     
     
       76. The method of manufacturing a functional transparent module of  claim 72  wherein the step of combining comprises the steps of disconnecting one or more solder- dot connections for the primary parts to isolated failed I/O line segments and of selectively connecting replacement line segments of said backup part.   
     
     
       77. The method of manufacturing a fully functional memory module of  claim 72  wherein the step of combining comprises bit patching to replace a failed I/O line segment of a primary part with an operational segment of said backup part. 
     
     
       78. The method of  claim 72  wherein the step of combining comprises the steps of selectively interrupting a failed I/O segment output connection of a primary part and replacing the interrupted I/O segment with a selected working I/O line segment of said backup part. 
     
     
       79. A transparent, fully functional memory module fabricated in accordance with the method of  claim 78 . 
     
     
       80. The method of  claim 72  wherein the step of combining comprises bit steering to replace a failed I/O line segment of a primary part with an operable segment of said backup part. 
     
     
       81. The method of  claim 72  wherein the step of combining comprises the steps of electrically interrupting an output of a failed I/O segment of said primary part and replacing the interrupted output segment with an electrical jumper to connect a selected working I/O output segment of said backup part. 
     
     
       82. A fully operational transparent memory module including primary parts and partially defective backup parts wherein said primary parts and said backup parts have been functionally tested and classified into a plurality of groups according to working I/O segments of said primary part and said backup parts, comprising:
   at least one primary part, said primary part having at least one failed output segment,        at least one partially defective backup part, said backup part having a different group classification than said primary part to facilitate replacement of failed output segments of said primary part,        a printed circuit module board having a pattern of conductive lines for forming electrical connections to the I/O output segments of said primary part, and        connector for selectively interrupting output segments of said primary part and for replacement thereof with a working line segment of said backup part.     
     
     
       83. The transparent memory module of  claim 82  wherein said connector means comprises a solder- dot connector means for selectively replacing failed primary part output segments with a working output segment of said backup part.   
     
     
       84. The transparent memory module of  claim 82  wherein said connector means comprises an electrical jumper connection on said printed circuit board. 
     
     
       85. The transparent memory module of  claim 82  wherein said connector means comprises an optimized bit patching means for replacing a failed output segment of said primary part with a working output segment of said backup part. 
     
     
       86. The transparent memory module of  claim 82  wherein said connector means comprises an optimized bit steering means for replacing a failed output line segment of said primary part with a working output segment of said backup part. 
     
     
       87. The method of  claim 1  wherein the combination of working segments comprises bit patching to replace failed I/O data lines with working I/O data lines of said backup memory part. 
     
     
       88. A memory module formed by the method described in  claim 87 . 
     
     
       89. The method of  claim 1  wherein the combination of working segments comprises bit steering means to replace failed I/O data lines of said primary part with working I/O data lines of said backup memory part. 
     
     
       90. The method of  claim 12  wherein the step of substituting comprises bit patching to replace failed I/O data line segments of said primary parts with selected operable I/O data line segments of said backup memory parts. 
     
     
       91. A memory module formed by the method described in  claim 90 . 
     
     
       92. The method of  claim 12  wherein the step of substituting comprises bit steering to replace failed I/O data line segments of said primary parts with selected operable I/O data line segments of said backup memory parts. 
     
     
       93. A method for patching primary memory parts of a memory module with segments of partially defective backup memory parts to produce a fully operational transparent memory module, said method comprising the steps of:
   performing a wafer test on a plurality of independent memory die,        identifying the respective working and non - working segments in each of said memory die,        packaging said plurality of memory die into primary and backup memory parts according to working and non - working segments,        selecting packaged parts for assembly on a printed circuit type board,        assembling the selected parts on said printed circuit board in accordance with test data identifying working segments of said parts,        selectively connecting output segments of the primary memory parts to said printed circuit board connectors,        subjecting the assembled primary parts to a full function circuit test to determine any failed output bits,        generating patching instructions to optimize repair of any failed output bits of said primary parts,        disconnecting any failed output bits of said primary parts in accordance with said test results, and        substituting working segments of said backup parts for failed bits of said primary parts in accordance with said patching instructions.     
     
     
       94. The method of  claim 93  wherein the step of substituting comprises bit patching to replace failed output bits of said primary parts with working segments of said backup parts. 
     
     
       95. A transparent, fully functional memory module fabricated in accordance with the method of  claim 94 . 
     
     
       96. The method of  claim 93  wherein the step of substituting comprises bit steering to replace failed output bits of said primary parts with working output bit segments of said backup parts. 
     
     
       97. A SIMM memory module made up of primary parts and partially defective backup parts, comprising:
   at least two primary parts with at least one of the primary parts having at least one line failure,        a plurality of partially defective independent backup parts,        a printed circuit module board having conductive strips on at least one surface of said board, and        connector means on said board for selectively disconnecting failed primary part lines to facilitate replacement thereof by substitute lines of said partially defective backup parts having an equivalent function as the failed line whereby the repaired memory module is fully functional and transparent to a user.     
     
     
       98. The SIMM memory module of  claim 97  wherein the connector means comprises an optimal bit patching means for replacing a failed primary part line with a substitute line from said backup part having the equivalent function as the failed line whereby the repaired memory module is fully functional and transparent to a user. 
     
     
       99. The SIMM memory module of  claim 97  wherein the connector means comprises an optimal bit steering means for replacing a failed primary part line with a substitute line from said backup part having the equivalent function as the failed line whereby the repaired memory module is fully functional and transparent to a user. 
     
     
       100. A chip- on - board memory module made up of a plurality of primary die parts and a plurality of partially defective backup die parts, comprising:      a printed circuit board having a plurality of conductors arranged on at least one surface for supporting said primary die parts and said backup die parts,        at least one primary die part mounted on said printed circuit board and connected to selected ones of said conductors and said primary die part having at least one failed line,        a plurality of partially defective backup die parts mounted on said printed circuit board in accordance with predetermined working and non - working line segments data,        means for identifying the respective working and non - working lines of said primary and backup die parts, and        connector means for selectively optimizing replacement of a non - working line of said primary part with a working line of said backup part having the equivalent function as said failed line so that the repaired memory module is fully functional and transparent to a user.     
     
     
       101. The memory module of  claim 100  wherein said connector means comprises an optimal bit patching means for replacing said failed non- working line of said primary part with a working line of one of said backup parts having an equivalent function as said failed line so the repaired memory module is fully functional and transparent to a user.   
     
     
       102. The memory module of  claim 100  wherein said connector means comprises an optimal bit steering means for replacing said failed non- working line of said primary part with a working line of one of said backup parts having the equivalent function as said failed line so the repaired memory module is fully functional and transparent to a user.   
     
     
       103. A semiconductor memory module fabricated to facilitate repair of defective components, the memory module comprising:
   a printed circuit - type board having a plurality of conductive pathways on at least one surface thereof and individual pathways being connected to I/O lines of said board,        at least one primary memory die part mounted on said printed circuit board having individual leads thereof connected to individual ones of said conductive pathways,        a plurality of independent partially defective backup memory die parts being mounted on said printed circuit board in positions determined in accordance with pre - assembly die test data to optimize backup capabilities of said backup memory die parts, and        bit patching means for selectively rerouting ones of said conductive pathways to selectively replace a non - working I/O line of said primary memory die part with a working I/O line of one of said backup memory die parts having an equivalent function as said failed I/O line to form a fully functional memory module.     
     
     
       104. The semiconductor memory module of  claim 103  wherein said bit patching means comprises connector means for increasing the electrical resistance of failed I/O lines to be replaced with working I/O lines of said backup die parts. 
     
     
       105. The memory module of  claim 104  wherein said bit steering means comprises connector means for selectively electrically interrupting failed I/O lines of said primary die part and for selectively connecting as replacement therefore a working I/O line of one of said backup die parts. 
     
     
       106. The memory module of  claim 103  wherein said backup memory die parts each have different group classifications determined by pre- assembly test data to facilitate replacement of failed I/O lines of said primary die part.   
     
     
       107. A semiconductor memory module fabricated to facilitate repair of defective components, the memory module comprising:
   a printed circuit - type board having a plurality of conductive pathways on at least one surface thereof and the individual pathways being connected to I/O lines of said board,        at least one primary memory die part mounted on said printed circuit board with predetermined leads electrically connected to pre - selected ones of said conductive pathways,        a plurality of independent partially defective backup memory die parts positioned on said printed circuit board in accordance with pre - assembly die test data to optimize backup capabilities of said mounted backup die parts, and        bit steering means for selectively combining working I/O lines of ones of said backup memory die parts and for electrically connecting said selected working I/O lines to replace non - working I/O lines of said primary die part to form thereby a fully functional memory module.     
     
     
       108. The semiconductor memory module of  claim 107  wherein said bit steering means comprises connector means for increasing the electrical resistance of failed I/O lines to be replaced with working I/O lines of said backup die parts. 
     
     
       109. The memory module of  claim 108  wherein said bit steering means comprises connector means for selectively electrically interrupting failed I/O lines of said primary die part and for selectively connecting as replacement a working I/O line of said backup memory die part.