Configurable cache allowing cache-type and buffer-type access

Abstract

A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

1. A memory storage system for storing recently accessed data from a main memory in a computer system, said memory storage system comprising:
 a memory storage area which is configurable into a cache portion and a buffer portion; and  
 means for storing indices corresponding to data stored in said memory storage area;  
 wherein when said cache portion is accessed by a given address, said index storage means is also accessed by said address to check if said data accessed from said cache portion is valid and when said buffer portion is accessed by said given address, said index storage means is not checked.  
 
     
     
       2. The memory system as described in  claim 1  wherein said index storage means further includes protection information indicating the access privilege of said given address into said main memory and when said index storage means is accessed by said given address, said protection information is concatenated onto an address accessed from said index storage means by said given address and provided to a CPU. 
     
     
       3. The memory system as described in  claim 2 , wherein said protection information includes a field that defines a coherence state of data stored at said given address, wherein said coherence state indicates whether data stored at said given address may be read, written into, or replaced. 
     
     
       4. The memory system as described in  claim 2 , wherein said protection information includes a field that defines an access priority of said given address, wherein said access priority indicates the order at which said given address is accessed with respect to other accesses in said memory system. 
     
     
       5. The memory system as described in  claim 2  wherein said protection information includes a field for indicating when a detail exception should occur. 
     
     
       6. The memory system as described in  claim 2  wherein said protection information includes a field that defines a cache control condition of said given address, wherein said cache control condition indicates states of said data stored in said given address including a cache coherent state, a non-allocated state, and a physical state. 
     
     
       7. A memory system as described in  claim 1 , wherein said given address includes an indication of whether an access is being performed on at least one of said cache portion and said buffer portion. 
     
     
       8. A method for storing recently accessed data from a main memory in a computer system, comprising the steps of:
 configuring a memory storage area into a cache portion and a buffer portion; and  
 storing indices corresponding to data stored in said memory storage area;  
 wherein when said cache portion is accessed by a given address, said stored indices are also accessed by said given address to check if said data accessed from said cache portion is valid and when said buffer portion is accessed by said given address, said stored indices are not checked.  
 
     
     
       9. The method of  claim 8 , wherein said given address includes an indication of whether an access is being performed on at least one of said cache portion and said buffer portion. 
     
     
       10. The method of claim  9    14 , wherein said protection information includes a field that defines a coherence state of data stored at said given address, wherein said coherence state indicates whether data stored at said given address may be read, written into, or replaced. 
     
     
       11. The method of claim  9    14 , wherein said protection information includes a field that defines an access priority of said given address, wherein said access priority indicates the order at which said given address is accessed with respect to other accesses in said memory system. 
     
     
       12. The method of claim  9    14 , wherein said protection information includes a field for indicating when a detail exception should occur. 
     
     
       13. The method of claim  9    14 , wherein said protection information includes a field that defines a cache control condition of said given address, wherein said cache control condition indicates states of said data stored in said given address including a cache coherent state, a non-allocated state, and a physical state. 
     
     
       14. The method of  claim 8 , wherein said stored indices further include protection information indicating the access privilege of said given address into said main memory and when said stored indices are accessed by said given address, said protection information is concatenated onto an address accessed from said stored indices by said given address and provided to a CPU. 
     
     
       15. A computer-readable medium containing a program that performs the steps of:
 receiving an indication that a memory storage area has been configured into a cache portion and a buffer portion; and  
 storing indices corresponding to data stored in said memory storage area;  
 wherein when said cache portion is accessed by a given address, said stored indices are also accessed by said given address to check if said data accessed from said cache portion is valid and when said buffer portion is accessed by said given address, said stored indices are not checked.  
 
     
     
       16. The method  computer- readable medium  of  claim 15 , wherein said given address includes an indication of whether an access is being performed on at least one of said cache portion and said buffer portion. 
     
     
       17. The computer-readable medium of claim  16    21 , wherein said protection information includes a field that defines a coherence state of data stored at said given address, wherein said coherence state indicates whether data stored at said given address may be read, written into, or replaced. 
     
     
       18. The computer-readable medium of claim  16    21 , wherein said protection information includes a field that defines an access priority of said given address, wherein said access priority indicates the order at which said given address is accessed with respect to other accesses in said memory system. 
     
     
       19. The computer-readable medium of claim  16    21 , wherein said protection information includes a field for indicating when a detail exception should occur. 
     
     
       20. The computer-readable medium of claim  16    21 , wherein said protection information includes a field that defines a cache control condition of said given address, wherein said cache control condition indicates states of said data stored in said given address including a cache coherent state, a non-allocated state, and a physical state. 
     
     
       21. The computer-readable medium of  claim 15 , wherein said stored indices further include protection information indicating the access privilege of said given address into said main memory and when said stored indices are accessed by said given address, said protection information is concatenated onto an address accessed from said stored indices by said given address and provided to a CPU. 
     
     
       22. The memory storage system of  claim 1  further comprising:
   a compare unit coupled to compare said given address to the indices upon accessing the cache portion, and generate a cache hit if a match is found, and generate a cache miss if no match is found.     
     
     
       23. The memory storage system of  claim 1  configured so that an access to the cache portion results in an access to the main memory if a cache miss is detected, and an access to the buffer portion does not result in an access to the main memory. 
     
     
       24. The memory storage system of  claim 1  configured so that in an access to the cache portion the memory storage system determines whether an access to the main memory is required, and in an access to the buffer portion no access to the main memory is required. 
     
     
       25. The memory storage system of  claim 1  wherein buffer accesses have a fixed access time and cache accesses have a variable access time due to cache misses. 
     
     
       26. The memory storage system of  claim 1  wherein upon accessing the memory storage area, the memory storage area receives information indicating whether the access is a cache access or a buffer access. 
     
     
       27. The memory storage system of  claim 1  wherein the memory storage area is partitioned between the cache portion and the buffer portion in accordance with configuration information received by the memory storage system. 
     
     
       28. The memory storage system of  claim 27  wherein the memory storage area is partitioned into one of a predetermined number of combinations of cache portion size and buffer portion size in accordance with configuration information received by the memory storage system. 
     
     
       29. The memory storage system of  claim 28  wherein the configuration information is set in a status register when the computer system is configured by software. 
     
     
       30. The memory storage system of  claim 1  wherein depending on the desired partitioning of the memory storage area between the cache portion and the buffer portion corresponding address ranges are allocated to the cache portion and the buffer portion. 
     
     
       31. The method of  claim 8  further comprising the step of:
   upon accessing the cache portion, comparing said given address to the indices and generating a cache hit if a match is found, and generating a cache miss if no match is found.     
     
     
       32. The method of  claim 8  further comprising the step of:
   if a cache miss is detected in an access to the cache portion, accessing the main memory for transferring data to and from the main memory.     
     
     
       33. The method of  claim 8  wherein in an access to the cache portion the memory storage system determines whether an access to the main memory is required, and in an access to the buffer portion no access to the main memory is required. 
     
     
       34. The method of  claim 8  wherein buffer accesses have a fixed access time and cache accesses have a variable access time due to cache misses. 
     
     
       35. The method of  claim 8  further comprising the step of:
   upon accessing the memory storage area, receiving information indicating whether the access is a cache access or a buffer access.     
     
     
       36. The method of  claim 8  further comprising the step of:
   partitioning the memory storage area between the cache portion and the buffer portion in accordance with configuration information received by the memory storage system.     
     
     
       37. The method of  claim 8  further comprising the step of:
   partitioning the memory storage area into one of a predetermined number of combinations of cache portion size and buffer portion size in accordance with configuration information received by the memory storage system.     
     
     
       38. The method of  claim 37  further comprising the step of:
   setting the configuration information in a status register when the computer system is configured by software.     
     
     
       39. The method of  claim 37  further comprising the step of:
   allocating address ranges to the cache portion and the buffer portion in accordance with the partitioning of the memory storage area between the cache portion and the buffer portion.     
     
     
       40. A memory storage system operable to store information accessed by a processor, the memory storage system comprising:
   an access path operable to access a main memory; and        a memory storage area which is configurable into a cache portion and a buffer portion, wherein the memory storage system receives an address for accessing the memory storage area, said address including a field for indicating whether the access includes a cache access or a buffer access.     
     
     
       41. The memory storage system of  claim 40  wherein, in a cache access, if the memory storage system detects a cache miss the main memory is accessed for information transfer, and if a cache hit is detected the main memory is not accessed. 
     
     
       42. The memory storage system of  claim 40  further comprising:
   a cache tag memory configured to store indices corresponding to information stored in the memory storage area, wherein upon accessing the cache portion the cache tag memory is checked to determine whether the cache tag memory contains an index corresponding to the cache access.     
     
     
       43. The memory storage system of  claim 40  further comprising:
   a cache tag memory configured to store indices corresponding to information stored in the memory storage area; and        a compare unit adapted to compare an address corresponding to a cache access to the indices stored in the cache tag memory, and generate a cache hit if a match is found, and generate a cache miss if no match is found.     
     
     
       44. The memory storage system of  claim 40  configured so that a cache access results in an access to the main memory if a cache miss is detected, and a buffer access does not result in an access to the main memory. 
     
     
       45. The memory storage system of  claim 40  configured so that, in a cache access, the memory storage system determines whether an access to the main memory is required, and in a buffer access no access to the main memory is required. 
     
     
       46. The memory storage system of  claim 40  wherein buffer accesses have a fixed access time and cache accesses have a variable access time due to cache misses. 
     
     
       47. The memory storage system of  claim 40  wherein the cache portion is further operable to store information transferred to the main memory. 
     
     
       48. The memory storage system of  claim 40  wherein the memory storage area is partitioned between the cache portion and the buffer portion in accordance with configuration information received by the memory storage system. 
     
     
       49. The memory storage system of  claim 48  wherein the configuration information partitions the memory storage area into one of a predetermined number of combinations of cache portion size and buffer portion size. 
     
     
       50. The memory storage system of  claim 48  wherein the configuration information is set in a status register when the computer system is configured by software. 
     
     
       51. The memory storage system of  claim 40  wherein, depending on the desired partitioning of the memory storage area between the cache portion and the buffer portion, corresponding address ranges are allocated to the cache portion and the buffer portion. 
     
     
       52. The memory storage system of  claim 40 , wherein an address bit in the address indicates whether the access is a cache access or a buffer access. 
     
     
       53. The memory storage system of  claim 40  configured to receive an address within an address space divided into a cache address space portion and a buffer address space portion. 
     
     
       54. The memory storage system of  claim 53  wherein the address space is divided into the cache address space portion and the buffer address space portion in accordance with at least the state of an address bit within the address space. 
     
     
       55. The memory storage system of  claim 40  wherein the memory storage area is partitioned between the cache portion and the buffer portion in accordance with configuration information received by the memory storage system, and wherein at least a portion of said address is modified in accordance with the configuration information to produce a modified address provided to the memory storage area. 
     
     
       56. The memory storage system of  claim 55  wherein a portion of the address is provided to the memory storage area without modification. 
     
     
       57. The memory storage system of  claim 55  wherein the modified address is provided to the cache portion of the memory storage area. 
     
     
       58. The memory storage system of  claim 55  wherein the modified address is used to access the entire memory storage area for accesses within the buffer address space portion. 
     
     
       59. The memory storage system of  claim 40  wherein said stored information comprises instructions. 
     
     
       60. The memory storage system of  claim 40  wherein said stored information comprises combined data and instructions. 
     
     
       61. A processor operable to simultaneously execute multiple threads and comprising the memory storage system of  claim 40 . 
     
     
       62. A memory storage system operable to store information accessed by a processor, the memory storage system comprising:
   an access path operable to access a main memory; and        a memory storage area which is configurable into a cache portion and a buffer portion in accordance with configuration information received by the memory storage system, wherein an address received by the memory storage system is modified in accordance with the configuration information to produce a modified address provided to the memory storage area.     
     
     
       63. A memory storage system operable to store information accessed by a processor, the memory storage system comprising:
   an access path operable to access a main memory; and        a memory storage area which is configurable into a cache portion and a buffer portion in accordance with configuration information received by the memory storage system,        wherein the memory storage system receives an address for accessing the memory storage area, said address being within an address space divided into a cache address space portion and a buffer address space portion, and the address including a field for indicating whether the access to the memory storage area is a cache access or a buffer access, and        wherein a portion of the address is modified in accordance with the configuration information to produce a modified address, the modified address together with an un - modified portion of the address being provided to the memory storage area.     
     
     
       64. A memory storage system operable to store information accessed by a processor, the memory storage system comprising:
   an access path operable to access a main memory;        a memory storage area which is configurable into a cache portion and a buffer portion; and        a cache tag memory configured to store indices corresponding to information stored in the memory storage area,        wherein the memory storage system receives an address for accessing the memory storage area, said address including a field for indicating whether the access is a cache access or a buffer access, wherein a cache access results in an access to the main memory if the cache tag memory does not contain an index corresponding to the cache access, and a buffer access does not result in an access to the main memory.