Multiple network protocol encoder/decoder and data processor

Abstract

A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine reacts accordingly to the pertinent data, and any data that are required by more than one data state machine is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location with a pointer designating such data (thereby ensuring minimal memory usage). Resulting display data are immediately passed to a display controller. Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.

1. An apparatus for decoding and encoding network protocols and data, comprising:
 a network protocol layer module for receiving and transmitting network packets and for encoding and decoding network packets bytes  which comprise packet data;  
 a data handler module for exchanging said packet data with said network protocol layer module and for processing a  at least one  specific data type or protocol; 
 a memory control module in communication with said data handler module for arbitrating memory accesses and for providing display data ; and  
 an operating system (o.s.)at least one state machine module that is optimized for a single selected network protocol, said o.s.at least one state machine module in communication with said data handler module and providing resource control and system and user interfaces ;  
 wherein said network protocol layer module, said data handler module, said memory control module, and said operating system (o.s.)  at least one state machine module comprise corresponding dedicated hardware structures that are implemented in hardware  gate level circuitry.  
 
     
     
       2. The apparatus of  claim 1 , wherein said network protocol layer module comprises a plurality of state machines representing different network protocols  stacks. 
     
     
       3. The apparatus of claim  2    1 , wherein said network protocol layer module implements one or more of the following network protocols: Point to Point Protocol (PPP), Internetwork Packet (IP), Transmission Control Protocol (TCP), Raw Socket, and/or User Datagram Protocol (UDP). 
     
     
       4. The apparatus of claim  2    1 , wherein said network packets bytes  are processed in real time. 
     
     
       5. The apparatus of claim  2    1 , wherein said network packets bytes  are processed concurrently. 
     
     
       6. The apparatus of claim  2    1 , wherein said network packets bytes  are processed byte- serially. 
     
     
       7. The apparatus of  claim 1 , wherein any data required more than once by a specific said state machine is placed in a specific memory location with a pointer designating said memory location. 
     
     
       8. The apparatus of  claim 1 , wherein said data handler module comprises at least one state machine which processes a specific data type. 
     
     
       9. The apparatus of  claim 8 , wherein said data handler module processes one or more of the following protocols: Hypertext Transfer Protocol (HTTP), Hypertext Markup Language (HTML), Post Office Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer Protocol (SMTP), Joint Photographic Experts Group (JPEG), Graphics Interchange Format (GIF), and/or Java language. 
     
     
       10. The apparatus of  claim 8 , wherein said data type is processed in real time. 
     
     
       11. The apparatus of  claim 8 , wherein said data type is processed concurrently. 
     
     
       12. The apparatus of  claim 8 , wherein said data type is processed byte  serially. 
     
     
       13. The apparatus of  claim 8 , wherein any data shared by said at least one state machine or required more than once by a specific said state machine is placed in a specific memory location with a pointer designating said memory location. 
     
     
       14. The apparatus of  claim 8 , wherein any data shared by said at least one state machine is provided to said state machine(s) concurrently. 
     
     
       15. The apparatus of  claim 1 , wherein said memory control module arbitrates all memory accesses. 
     
     
       16. The apparatus of  claim 1 , wherein said memory control module contains a Unified Memory Architecture (UMA) which allows a system memory and a video memory to reside in a same memory area. 
     
     
       17. The apparatus of  claim 1 , wherein said memory control module is comprised of one or more arbiter logic blocks where an arbiter block arbitrates according to a dynamic rotating algorithm between two devices. 
     
     
       18. The apparatus of  claim 1 , wherein said memory control module is comprised of one or more arbiter logic blocks arranged in such a manner as to give a fixed weighted priority to each of a plurality of devices for memory access based on a given arbiter tree structure. 
     
     
       19. The apparatus of  claim 1 , wherein said o.s.  further comprising an arbitrator state machine that acts as an arbitrator between said network protocol layer module, said data handler module, and said memory control module for resource control, system and user interface. 
     
     
       20. The apparatus of  claim 1 , further comprising:
 a display controller.  
 
     
     
       21. The apparatus of  claim 20 , wherein said display controller controls one of the following types of displays: VGA, television, Liquid Crystal Display (LCD), or Light Emitting Diode (LED). 
     
     
       22. The apparatus of  claim 1 , wherein said apparatus acts as an interface between Internet signals and application products by processing Internet signals in real- time and sending said processed Internet signals to said application products . 
     
     
       23. A process for decoding and encoding network protocols and data, said process comprising the steps of:
 providing a network protocol layer module for receiving and transmitting network packets and for encoding and decoding network packets bytes  which comprise packet data;  
 providing a data handler module for exchanging said packet data with said network protocol layer module and for processing a  at least one specific data type or protocol;  
 providing a memory control module in communication with said data handler module for arbitrating memory accesses and for providing display data ; and  
 providing an operating system (o.s.)  at least one state machine module that is implemented in hardware and that is  optimized for a single selected network protocol, said o.s.  at least one state machine module in communication with said data handler module and providing resource control and system and user interfaces ;  
 wherein said network protocol layer module, said data handler module, said memory control module, and said operating system (o.s.)  at least one state machine module comprise corresponding dedicated hardware structures that are implemented in hardware  gate level circuitry.  
 
     
     
       24. The process of  claim 23 , wherein said step of encoding and decoding network packet bytes  network protocol layer module further comprises the step of:
 representing different network protocols  stacks using a plurality of state machines.  
 
     
     
       25. The process of  claim 24 , wherein said step of encoding and decoding network packet bytes  network protocol layer module further comprises the step of:
 encoding and decoding one or more of the following network protocols: Point to Point Protocol (PPP), Internetwork Packet (IP), Transmission Control Protocol (TCP), Raw Socket, and/or User Datagram Protocol (UDP).  
 
     
     
       26. The process of  claim 23 , wherein said network protocol layer module step of encoding and decoding network packet bytes  further comprises the step of:
 processing network packets bytes  in real time.  
 
     
     
       27. The process of  claim 23 , wherein said step of encoding and decoding network packet bytes  network protocol layer module further comprises the step of:
 processing network packets bytes  concurrently.  
 
     
     
       28. The process of  claim 23 , wherein said step of encoding and decoding network packet bytes  network protocol layer module further comprise the step s  of:
 processing network packet bytes  packets in a byte  serial fashion.  
 
     
     
       29. The process of  claim 23 , wherein said step of processing packet data bytes  data handler module further comprises the step of:
 processing specific data type(s) using at least one state machine.  
 
     
     
       30. The process of  claim 29 , wherein said step of processing packet data bytes  data handler module further comprises the step of:
 use of a CRC algorithm to decode data fields.  
 
     
     
       31. The process of  claim 29 , wherein said step of processing packet data bytes  data handler module further comprises the step of:
 processing one or more of the following protocols: Hypertext Transfer Protocol (HTTP), Hypertext Markup Language (HTML), Post Office Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer Protocol (SMTP), Joint Photographic Experts Group (JPEG), Graphics Interchange Format (GIF), and/or Java language.  
 
     
     
       32. The process of  claim 29 , wherein said step of processing packet data bytes  data handler module further comprises the step of:
 processing packet data bytes  in real time.  
 
     
     
       33. The process of  claim 29 , wherein said step of processing packet data bytes  data handler module further comprises the step of:
 processing packet data bytes  concurrently.  
 
     
     
       34. The process of  claim 29 , wherein said step of processing packet data bytes  data handler module further comprises the step of:
 processing packet data bytes  in a byte  serial fashion.  
 
     
     
       35. The process of  claim 29 , wherein said step of processing packet data bytes  data handler module further comprises the step of:
 placing any data more than once by a specific one of said at least one state machine in a specific memory location with a pointer designating said memory location.  
 
     
     
       36. The process of  claim 23 , wherein said step of controlling memory accesses further comprises the step of:  memory control module arbitrating es all memory accesses. 
     
     
       37. The process of  claim 23 , wherein said step of controlling memory accesses further comprises the step of:  memory control module allowing s a system memory and a video memory to reside in a same memory area using a Unified Memory Architecture (UMA). 
     
     
       38. The process of  claim 23 , wherein said step of controlling state machine sequencing  further comprises ing the step of:
 arbitrating between said step of encoding and decoding network packet bytes  network protocol layer module, said step of processing packet data bytes  data handler module, and said step of controlling memory accesses  memory control module for resource control, system and user interface.  
 
     
     
       39. The process of  claim 23 , wherein said step of controlling state machine sequencing  further comprises ing the step of:
 interpreting system and user input for the purpose of controlling data handler modules and network protocol layer modules.  
 
     
     
       40. The process of  claim 23 , further comprising the step of:
 displaying output data.  
 
     
     
       41. The process of  claim 40 , wherein said step of displaying output data further comprises the step of:
 controlling one of the following types of displays: VGA, television, Liquid Crystal Display (LCD), or Light Emitting Diode (LED).  
 
     
     
       42. The process of  claim 23 , wherein said process is used to implement an interface between Internet signals and application products by processing Internet signals in real- time and sending said processed Internet signals to said application products . 
     
     
       43. The apparatus of  claim 1 , wherein said memory control module provides display data. 
     
     
       44. The process of  claim 23 , wherein said memory control module provides display data.